Patents by Inventor Frederico C. Pratas

Frederico C. Pratas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230020571
    Abstract: An apparatus and method are described for distributed and cooperative computation in artificial neural networks. For example, one embodiment of an apparatus comprises: an input/output (I/O) interface; a plurality of processing units communicatively coupled to the I/O interface to receive data for input neurons and synaptic weights associated with each of the input neurons, each of the plurality of processing units to process at least a portion of the data for the input neurons and synaptic weights to generate partial results; and an interconnect communicatively coupling the plurality of processing units, each of the processing units to share the partial results with one or more other processing units over the interconnect, the other processing units using the partial results to generate additional partial results or final results. The processing units may share data including input neurons and weights over the shared input bus.
    Type: Application
    Filed: September 20, 2022
    Publication date: January 19, 2023
    Inventors: Frederico C. PRATAS, Ayose J. FALCON, Marc LUPON, Fernando LATORRE, Pedro LOPEZ, Enric HERRERO ABELLANAS, Georgios TOURNAVITIS
  • Publication number: 20210326405
    Abstract: An apparatus and method are described for distributed and cooperative computation in artificial neural networks. For example, one embodiment of an apparatus comprises: an input/output (I/O) interface; a plurality of processing units communicatively coupled to the I/O interface to receive data for input neurons and synaptic weights associated with each of the input neurons, each of the plurality of processing units to process at least a portion of the data for the input neurons and synaptic weights to generate partial results; and an interconnect communicatively coupling the plurality of processing units, each of the processing units to share the partial results with one or more other processing units over the interconnect, the other processing units using the partial results to generate additional partial results or final results. The processing units may share data including input neurons and weights over the shared input bus.
    Type: Application
    Filed: May 3, 2021
    Publication date: October 21, 2021
    Inventors: Frederico C. PRATAS, Ayose J. FALCON, Marc LUPON, Fernando LATORRE, Pedro LOPEZ, Enric HERRERO ABELLANAS, Georgios TOURNAVITIS
  • Patent number: 10997273
    Abstract: An apparatus and method are described for distributed and cooperative computation in artificial neural networks. For example, one embodiment of an apparatus comprises: an input/output (I/O) interface; a plurality of processing units communicatively coupled to the I/O interface to receive data for input neurons and synaptic weights associated with each of the input neurons, each of the plurality of processing units to process at least a portion of the data for the input neurons and synaptic weights to generate partial results; and an interconnect communicatively coupling the plurality of processing units, each of the processing units to share the partial results with one or more other processing units over the interconnect, the other processing units using the partial results to generate additional partial results or final results. The processing units may share data including input neurons and weights over the shared input bus.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: May 4, 2021
    Assignee: Intel Corporation
    Inventors: Frederico C. Pratas, Ayose J. Falcon, Marc Lupon, Fernando Latorre, Pedro Lopez, Enric Herrero Abellanas, Georgios Tournavitis
  • Patent number: 10402468
    Abstract: Systems and methods for performing convolution operations. An example processing system comprises: a processing core; and a convolver unit to apply a convolution filter to a plurality of input data elements represented by a two-dimensional array, the convolver unit comprising a plurality of multipliers coupled to two or more sets of latches, wherein each set of latches is to store a plurality of data elements of a respective one-dimensional section of the two-dimensional array.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: September 3, 2019
    Assignee: Intel Corporation
    Inventors: Enric Herrero Abellanas, Marc Lupon, Ayose J. Falcon, Frederico C. Pratas, Fernando Latorre, Pedro Lopez
  • Publication number: 20180329867
    Abstract: Systems and methods for performing convolution operations. An example processing system comprises: a processing core; and a convolver unit to apply a convolution filter to a plurality of input data elements represented by a two-dimensional array, the convolver unit comprising a plurality of multipliers coupled to two or more sets of latches, wherein each set of latches is to store a plurality of data elements of a respective one-dimensional section of the two-dimensional array.
    Type: Application
    Filed: April 9, 2018
    Publication date: November 15, 2018
    Inventors: Enric Herrero Abellanas, Marc Lupon, Ayose J. Falcon, Frederico C. Pratas, Fernando Latorre, Pedro Lopez
  • Patent number: 10002108
    Abstract: Systems and methods for performing convolution operations. An example processing system comprises: a processing core; and a convolver unit to apply a convolution filter to a plurality of input data elements represented by a two-dimensional array, the convolver unit comprising a plurality of multipliers coupled to two or more sets of latches, wherein each set of latches is to store a plurality of data elements of a respective one-dimensional section of the two-dimensional array.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: June 19, 2018
    Assignee: Intel Corporation
    Inventors: Enric Herrero Abellanas, Marc Lupon, Ayose J. Falcon, Frederico C. Pratas, Fernando Latorre, Pedro Lopez
  • Patent number: 9971540
    Abstract: A storage device and method are described for performing convolution operations. For example, one embodiment of an apparatus to perform convolution operations comprises a plurality of processing units to execute convolution operations on input data and partial results; a unified scratchpad memory comprising a plurality of memory banks communicatively coupled to the plurality of processing units through a plurality of read/write ports, each of the plurality of memory banks partitioned to store both the input data and partial results; a control unit to allocate the input data and partial results to the memory banks to ensure a minimum quality of service in accordance with the specified number of read/write ports and the specified convolution operation to be performed.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: May 15, 2018
    Assignee: INTEL CORPORATION
    Inventors: Enric Herrero Abellanas, Georgios Tournavitis, Frederico C. Pratas, Marc Lupon, Fernando Latorre, Pedro Lopez, Ayose J. Falcon
  • Publication number: 20170277658
    Abstract: An apparatus and method are described for distributed and cooperative computation in artificial neural networks. For example, one embodiment of an apparatus comprises: an input/output (I/O) interface; a plurality of processing units communicatively coupled to the I/O interface to receive data for input neurons and synaptic weights associated with each of the input neurons, each of the plurality of processing units to process at least a portion of the data for the input neurons and synaptic weights to generate partial results; and an interconnect communicatively coupling the plurality of processing units, each of the processing units to share the partial results with one or more other processing units over the interconnect, the other processing units using the partial results to generate additional partial results or final results. The processing units may share data including input neurons and weights over the shared input bus.
    Type: Application
    Filed: November 19, 2015
    Publication date: September 28, 2017
    Inventors: Frederico C. PRATAS, Ayose J. FALCON, Marc LUPON, Fernando LATORRE, Pedro LOPEZ, Enric HERRERO ABELLANAS, Georgios TOURNAVITIS
  • Publication number: 20170220524
    Abstract: Systems and methods for performing convolution operations. An example processing system comprises: a processing core; and a convolver unit to apply a convolution filter to a plurality of input data elements represented by a two-dimensional array, the convolver unit comprising a plurality of multipliers coupled to two or more sets of latches, wherein each set of latches is to store a plurality of data elements of a respective one-dimensional section of the two-dimensional array.
    Type: Application
    Filed: March 9, 2017
    Publication date: August 3, 2017
    Inventors: Enric Herrero Abellanas, Marc Lupon, Ayose J. Falcon, Frederico C. Pratas, Fernando Latorre, Pedro Lopez
  • Patent number: 9613001
    Abstract: Systems and methods for performing convolution operations. An example processing system comprises: a processing core; and a convolver unit to apply a convolution filter to a plurality of input data elements represented by a two-dimensional array, the convolver unit comprising a plurality of multipliers coupled to two or more sets of latches, wherein each set of latches is to store a plurality of data elements of a respective one-dimensional section of the two-dimensional array.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: April 4, 2017
    Assignee: Intel Corporation
    Inventors: Enric Herrero Abellanas, Marc Lupon, Ayose J. Falcon, Frederico C. Pratas, Fernando Latorre, Pedro Lopez
  • Publication number: 20160179434
    Abstract: A storage device and method are described for performing convolution operations. For example, one embodiment of an apparatus to perform convolution operations comprises a plurality of processing units to execute convolution operations on input data and partial results; a unified scratchpad memory comprising a plurality of memory banks communicatively coupled to the plurality of processing units through a plurality of read/write ports, each of the plurality of memory banks partitioned to store both the input data and partial results; a control unit to allocate the input data and partial results to the memory banks to ensure a minimum quality of service in accordance with the specified number of read/write ports and the specified convolution operation to be performed.
    Type: Application
    Filed: September 22, 2015
    Publication date: June 23, 2016
    Inventors: ENRIC HERRERO ABELLANAS, GEORGIOS TOURNAVITIS, FREDERICO C. PRATAS, MARC LUPON, FERNANDO LATORRE, PEDRO LOPEZ, AYOSE J. FALCON
  • Publication number: 20160026912
    Abstract: A processor includes a processor core and a calculation circuit. The processor core includes logic determine a set of weights for use in a convolutional neural network (CNN) calculation and scale up the weights using a scale value. The calculation circuit includes logic to receive the scale value, the set of weights, and a set of input values, wherein each input value and associated weight of a same fixed size. The calculation circuit also includes logic to determine results from convolutional neural network (CNN) calculations based upon the set of weights applied to the set of input values, scale down the results using the scale value, truncate the scaled down results to the fixed size, and communicatively couple the truncated results to an output for a layer of the CNN.
    Type: Application
    Filed: July 22, 2014
    Publication date: January 28, 2016
    Inventors: Ayose J. Falcon, Marc Lupon, Enric Herrero Abellanas, Pedro Lopez, Fernando Latorre, Frederico C. Pratas, Georgios Tournavitis
  • Publication number: 20150178246
    Abstract: Systems and methods for performing convolution operations. An example processing system comprises: a processing core; and a convolver unit to apply a convolution filter to a plurality of input data elements represented by a two-dimensional array, the convolver unit comprising a plurality of multipliers coupled to two or more sets of latches, wherein each set of latches is to store a plurality of data elements of a respective one-dimensional section of the two-dimensional array.
    Type: Application
    Filed: December 20, 2013
    Publication date: June 25, 2015
    Inventors: Enric Herrero Abellanas, Marc Lupon, Ayose J. Falcon, Frederico C. Pratas, Fernando Latorre, Pedro Lopez