Abstract: Disclosed is a method for operating a cache memory. In response to a write transaction, data is written to a location in a foreground memory that is part of the cache. A modified bit is set in the foreground memory indicating that the data must be written back to main memory. A registration bit is checked in the foreground memory location to determine whether the address is registered. The location of the foreground memory is written to a registration memory in the cache if the registration bit is not set. The registration bit is set in the foreground memory, in conjunction with writing the address of the memory location to the registration memory, to indicate that the address has been registered. In response to a subsequent transaction, the foreground memory location can be selected to store new required data. The modified bit is checked to determine whether the data stored in the foreground memory location must be written back to main memory before the location can be used to store the new data.

Abstract: A masking comparison circuit outputs a signal "non-correspondence" if two binary signals received are unequal. However, there are provided masking means for masking this non-correspondence signal unless both binary signals for some time have been stable and, moreover, different. A comparison circuit of this kind forms part of, for example a data processing device based on redundancy.

Abstract: An end-around coupled chain of n bit counter stages, including an inversion element in the chain, employs a detection/correction mechanism for an invalid counter position. A "1,0" state pair is detected in the highest order two bit stages and the simultaneous occurrence of any "1" state in an adjacent group of at least J stages (where J equals the integer part of the number of stages divided by three) indicates an invalid counter position. At least said adjacent group of bit stages is set to "0" in response to the detection of an invalid counter position.