Patents by Inventor Frederik Leys

Frederik Leys has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8962369
    Abstract: A method for introducing species into a strained semiconductor layer comprising: providing a substrate comprising a first region comprising an exposed strained semiconductor layer, loading the substrate in a reaction chamber, then forming a conformal first species containing-layer by vapor phase deposition (VPD) at least on the exposed strained semiconductor layer, and thereafter performing a thermal treatment, thereby diffusing at least part of the first species from the first species-containing layer into the strained semiconductor layer and activating at least part of the diffused first species in the strained semiconductor layer.
    Type: Grant
    Filed: July 10, 2013
    Date of Patent: February 24, 2015
    Assignee: IMEC
    Inventors: Roger Loo, Frederik Leys, Matty Caymax
  • Publication number: 20140008727
    Abstract: A method for introducing species into a strained semiconductor layer comprising: providing a substrate comprising a first region comprising an exposed strained semiconductor layer, loading the substrate in a reaction chamber, then forming a conformal first species containing-layer by vapor phase deposition (VPD) at least on the exposed strained semiconductor layer, and thereafter performing a thermal treatment, thereby diffusing at least part of the first species from the first species-containing layer into the strained semiconductor layer and activating at least part of the diffused first species in the strained semiconductor layer.
    Type: Application
    Filed: July 10, 2013
    Publication date: January 9, 2014
    Inventors: Roger Loo, Frederik Leys, Matty Caymax
  • Patent number: 8507337
    Abstract: A method for introducing species into a strained semiconductor layer comprising: providing a substrate comprising a first region comprising an exposed strained semiconductor layer, loading the substrate in a reaction chamber, then forming a conformal first species containing-layer by vapor phase deposition (VPD) at least on the exposed strained semiconductor layer, and thereafter performing a thermal treatment, thereby diffusing at least part of the first species from the first species-containing layer into the strained semiconductor layer and activating at least part of the diffused first species in the strained semiconductor layer.
    Type: Grant
    Filed: July 6, 2009
    Date of Patent: August 13, 2013
    Assignee: IMEC
    Inventors: Roger Loo, Frederik Leys, Matty Caymax
  • Publication number: 20110169049
    Abstract: A method for introducing species into a strained semiconductor layer comprising: providing a substrate comprising a first region comprising an exposed strained semiconductor layer, loading the substrate in a reaction chamber, then forming a conformal first species containing-layer by vapor phase deposition (VPD) at least on the exposed strained semiconductor layer, and thereafter performing a thermal treatment, thereby diffusing at least part of the first species from the first species-containing layer into the strained semiconductor layer and activating at least part of the diffused first species in the strained semiconductor layer.
    Type: Application
    Filed: July 6, 2009
    Publication date: July 14, 2011
    Applicant: IMEC
    Inventors: Roger Loo, Frederik Leys, Matty Caymax
  • Patent number: 7737008
    Abstract: A method for forming at least one quantum dot at at least one predetermined location on a substrate is disclosed. In one aspect, the method comprises providing a layer of semiconductor material on an insulating layer on the substrate. The layer of semiconductor material is patterned so as to provide at least one line of semiconductor material having a width (wL) and having a local width variation at at least one predetermined location where the at least one quantum dot has to be formed. The local width variation has an amplitude (A) of between about 20 nm and 35 nm higher than the width wL of the at least one line. The at least one line is patterned to form at least one quantum dot. A design for a lithographic mask for use with the method and a method for making such a design are also disclosed.
    Type: Grant
    Filed: October 30, 2008
    Date of Patent: June 15, 2010
    Assignee: IMEC
    Inventors: Rita Rooyackers, Frederik Leys, Axel Nackaerts
  • Publication number: 20090137102
    Abstract: A method for forming at least one quantum dot at least one predetermined location on a substrate is disclosed. In one aspect, the method comprises providing a layer of semiconductor material on an insulating layer on the substrate. The layer of semiconductor material is patterned so as to provide at least one line of semiconductor material having a width (wL) and having a local width variation at least one predetermined location where the at least one quantum dot has to be formed. The local width variation has an amplitude (A) of between about 20 nm and 35 nm higher than the width wL of the at least one line. The at least one line is patterned to form at least one quantum dot. A design for a lithographic mask for use with the method and a method for making such a design are also disclosed.
    Type: Application
    Filed: October 30, 2008
    Publication date: May 28, 2009
    Applicant: Interuniversitair Microelektronica Centrum vzw (IMEC)
    Inventors: Rita Rooyackers, Frederik Leys, Axel Nackaerts
  • Publication number: 20080153266
    Abstract: A method of producing a semiconductor device using a selective epitaxial growth (SEG) process is disclosed. In one aspect, the method comprises providing a semiconductor substrate, forming a pattern of an insulation material on the semiconductor substrate, thereby defining a covered and non covered surface, performing a cleaning processing of the covered and non covered surface of the substrate having the insulating pattern defined, loading the substrate with the insulating pattern into a reaction chamber of an epitaxial reactor, and starting a selective epitaxial growth comprising an injection of at least one semiconductor source gas possibly with at least one first carrier gas in the reaction chamber of the epitaxial reactor. The method further comprises, prior to the selective epitaxial growth, the surface of the substrate is subjected in the reaction chamber to an in situ pre-treatment with the injection of a halogen containing etching gas possibly with a second carrier gas.
    Type: Application
    Filed: December 20, 2007
    Publication date: June 26, 2008
    Applicant: Interuniversitair Microeletronica Centrum (IMEC) VZW
    Inventors: Frederik Leys, Roger Loo, Matty Caymax
  • Publication number: 20060086950
    Abstract: The present invention is related to a method for making a passivated semiconductor substrate comprising the steps of providing a substrate surface comprising or consisting of mono-crystalline semiconductor material other than silicon and forming a silicon layer on the substrate surface, such that the silicon layer is substantially lattice matched to the mono-crystalline semiconductor material. It is also related to a semiconductor substrate passivated according to the method.
    Type: Application
    Filed: October 13, 2005
    Publication date: April 27, 2006
    Inventors: Matty Caymax, Renaud Bonzom, Frederik Leys, Marc Meuris