Abstract: A digital front-end circuit is disclosed. In one aspect, the circuit includes a filtering block for filtering received data. The filtering block has a first filter branch for filtering the received data in a first frequency band and a second filter branch for filtering the received data in a selected second frequency band. The second filter branch is in parallel with the first filter branch, is programmable and includes a block for resampling the received data. The front-end circuit also includes a circuit for performing synchronization and spectrum sensing on the received data, which is in connection with the output of the filtering block. The front-end circuit also includes a controller block for controlling the filtering block and the synchronization circuit.

Abstract: Disclosed is a method for selecting a design option for a Viterbi decoder model. In some embodiments, the method includes deriving a set of design options for a Viterbi decoder model by differentiating at least one design parameter, where the at least one design parameter comprises at least a first value for a look-ahead parameter. The method further includes performing an evaluation of each design option in the set of design options in a multi-dimensional design space and, based on the evaluation of each design option, selecting a design option in the set of design options that (i) satisfies a predetermined energy efficiency constraint and (ii) yields at least a second value for the look-ahead parameter, wherein the second value is greater than the first value and satisfies a predetermined area budget.

Abstract: A system for execution of a decoding method is disclosed. The system is capable of executing at least two data decoding methods which are different in underlying coding principle, wherein at least one of the data decoding methods requires data shuffling operations on the data. In one aspect, the system includes at least one application specific processor having an instruction set having arithmetic operators excluding multiplication, division and power. The processor is selected for execution of approximations of each of the at least two data decoding methods. The system also includes at least a first memory unit, e.g. background memory, for storing data. The system also includes a transfer unit for transferring data from the first memory unit towards the at least one programmable processor. The transfer unit includes a data shuffler. The system may also include a controller for controlling the data shuffler independent from the processor.

Abstract: A digital front-end circuit is disclosed. In one aspect, the circuit includes a filtering block for filtering received data. The filtering block has a first filter branch for filtering the received data in a first frequency band and a second filter branch for filtering the received data in a selected second frequency band. The second filter branch is in parallel with the first filter branch, is programmable and includes a block for resampling the received data. The front-end circuit also includes a circuit for performing synchronization and spectrum sensing on the received data, which is in connection with the output of the filtering block. The front-end circuit also includes a controller block for controlling the filtering block and the synchronization circuit.

Abstract: A system for execution of a decoding method is disclosed. The system is capable of executing at least two data decoding methods which are different in underlying coding principle, wherein at least one of the data decoding methods requires data shuffling operations on the data. In one aspect, the system includes at least one application specific processor having an instruction set having arithmetic operators excluding multiplication, division and power. The processor is selected for execution of approximations of each of the at least two data decoding methods. The system also includes at least a first memory unit, e.g. background memory, for storing data. The system also includes a transfer unit for transferring data from the first memory unit towards the at least one programmable processor. The transfer unit includes a data shuffler. The system may also include a controller for controlling the data shuffler independent from the processor.