Abstract: Provided are methods to reduce the thickness of a high-? layer needed in a DRAM capacitor and, thus, allow the cell electrodes to be larger, giving higher cell capacitance. A tantalum nitride (TaN) layer is introduced as a liner in the capacitor hole before a titanium nitride (TiN) electrode layer. The TaN layer converts to a thin layer of tantalum oxide (Ta2O5), which permits a reduction in the high-? layer thickness for the same capacitance versus leakage. Because this Ta2O5 is formed directly on the cell electrode, it ensures a low leakage film exists in the narrowest gaps even before the high-? layer is deposited.

Abstract: A method for forming an oxide layer includes forming at least a portion of a gate oxide layer on inner surfaces of an opening, forming a silicon nitride capping layer on the portion of the gate oxide layer, and performing a conversion process to at least partially oxidize the silicon nitride capping layer, forming a nitrogen-doped gate oxide layer.

Abstract: Provided is a DRAM device having a support layer to hold the bWL features before being filled with the electrode metal. The support layer keeps the structure supported from the top surface but does not prevent the gap fill. A temporary gap-fill material is first deposited in the bWL gaps and then recessed to expose the top edges. A support layer material is then deposited on the structure by plasma enhanced chemical vapor deposition (PECVD). The device is then patterned orthogonal and with pitch greater than the bWL pitch. The temporary gap-fill material is then removed, forming support beams comprising the support material. A metal can then be deposited to fill the bWL gaps under the support beams.

Abstract: The present technology includes vertical cell dynamic random-access memory (DRAM) structures with improve bit line capacitance. Structures include a plurality of lower bit lines arranged in a first horizontal direction in a first horizontal plane. Structures include a plurality of upper bit lines arranged in the first horizontal direction in a second horizontal plane, where the first horizontal plane is vertically spaced apart from the second horizontal plane. Structures include one or more word lines arranged in a second horizontal direction. Structures include one or more channels extending in a vertical direction that is generally orthogonal to the first horizontal direction and the second horizontal direction such that the plurality of lower bit lines and plurality of upper bit lines intersect with a source/drain region of the one or more channels, and the one or more word lines intersect with a gated region of the one or more channels.

Abstract: Semiconductor devices and methods of manufacturing the same are described. The methods form a 3D DRAM architecture that includes a semiconductor isolation bridge, eliminating a floating body effect. The method includes forming an epitaxial layer in a deep trench isolation opening and creating a semiconductor isolation bridge between adjacent deep trench isolation openings.

Abstract: A method of processing a metal layer for a semiconductor structure includes performing a metal surface recovery process to remove an oxidized or nitridized layer from a surface of the metal layer and recover a metal surface of the metal layer, performing a metal passivation process to passivate the metal surface of the metal layer and form a passivation layer, and performing an encapsulation layer deposition process to deposit an encapsulation layer on the passivation layer.

Abstract: The present technology includes methods and systems for forming advanced memory structures, and devices therefrom. Methods include forming a dummy material layer over a first sidewall, a second sidewall, and a bottom surface, of one or more features, where the first sidewall is spaced apart from the second sidewall and the bottom surface is disposed between the first sidewall and the second sidewall. Methods include filling a gap formed between the dummy material on the first sidewall and the low resistivity material on the second sidewall with a sacrificial isolation material. Methods include removing at least a portion of the bottom surface, exposing at least a portion of the dummy material and the sacrificial isolation material. Methods include removing the sacrificial isolation material and at least a portion of the dummy material and selectively depositing a conductive material on a remaining portion of the dummy material.

Abstract: Approaches for forming 3D DRAM cells are disclosed. One method may include forming a dielectric liner and a fill material within a plurality of lateral openings extending from a slot, wherein the plurality of lateral openings and the slot are formed in a carbon-doped stack of alternating first layers and second layers, and partially removing the dielectric liner from the plurality of lateral openings. The method may further include forming a sacrificial layer along the plurality of lateral openings and the slot, removing the sacrificial layer, and forming a gate dielectric along the plurality of lateral openings and the slot following removal of the sacrificial layer.

Abstract: Embodiments of the present disclosure generally relate to epitaxial film stacks and vapor deposition processes for preparing the epitaxial film stacks. In one or more embodiments, a multi-layered epitaxial stack is disposed on a substrate, and the multi-layered epitaxial stack contains a plurality of doped silicon-germanium and silicon mini-stacks. Each of the doped silicon germanium stack contains a doped-silicon-germanium layer disposed between a first silicon-germanium layer and a second silicon-germanium layer. Each of the doped-silicon-germanium layers independently contains a concentration of a dopant which may vary or be the same between each of the doped-silicon-germanium layers. The multi-layered epitaxial stack has a dopant gradient based on the concentration of the dopant within each of the doped-silicon-germanium layers such that the multi-layered epitaxial stack has a wafer bow value at a predetermined threshold.

Abstract: The present technology includes methods and systems for forming advanced memory structures, and devices therefrom. Methods include forming a dielectric material layer over a first sidewall, a second sidewall, and a bottom surface, of one or more features, where the first sidewall is spaced apart from the second sidewall and the bottom surface is disposed between the first sidewall and the second sidewall. Methods include depositing a low resistivity conductive material on the dielectric material layer on the first sidewall, the second sidewall, and the bottom surface. Methods include filling a gap formed between the low resistivity conductive material on the first sidewall and the low resistivity material on the second sidewall with a sacrificial isolation material. Methods include removing at least a portion of the bottom surface, exposing at least a portion of the low resistivity conductive material formed on the bottom surface and removing the sacrificial isolation material.

Abstract: Disclosed are DRAM devices and methods of forming DRAM devices. One non-limiting method may include recessing a plurality of vertical pillars of a dynamic random-access memory cell within each contact opening of a plurality of contact openings, and forming a selective epitaxial material over the plurality of vertical pillars while the dynamic random-access memory cell is maintained at a temperature below 500° C.

Abstract: A method for forming an oxide layer includes forming a protective interlayer oxide on sidewalls of a trench formed on a substrate, forming a silicon nitride layer on the protective interlayer oxide, by a plasma-enhanced atomic layer deposition (PE ALD) process utilizing nitrogen-containing process gas, the silicon nitride layer having a concentration gradient of nitrogen varying from high concentration away from the protective interlayer oxide to low concentration near the protective interlayer oxide, and performing a conversion process to oxidize the formed silicon nitride layer to at least partially convert the formed silicon nitride layer to a silicon oxide layer.

Abstract: Exemplary methods of manufacturing 2D DRAM and 3D DRAM devices include etching a portion of a low-k spacer material from a substrate. The methods may include exposing the remaining portion of the low-k spacer material of a 2D DRAM bit line to a carbon-containing precursor, to replenish the carbon content in the low-k spacer material. Additional methods may include exposing the remaining portion of the low-k spacer material of a 3D DRAM word line to a carbon-containing precursor to replenish the carbon content in the low-k spacer material. Further embodiments may include simultaneous treatment with ultraviolet (UV) radiation.

Abstract: The present technology includes methods and systems for forming advanced memory structures, and the resulting devices. Methods include forming a dielectric material layer over a first sidewall, a second sidewall, and a bottom wall, of one or more features, where the first sidewall is spaced apart from the second sidewall and the bottom wall is disposed between the first sidewall and the second sidewall. Methods include depositing a liner material directly on the dielectric material layer on the first sidewall, the second sidewall, and the bottom wall. Methods include removing at least a portion of the liner material from the bottom wall. Methods include selectively depositing a conductive material on a remaining portion of the liner material.

Abstract: A method for forming an oxide layer in a vertical channel structure includes performing a pre-clean process to remove contaminants on exposed surfaces of channel pillars extending in a first direction, performing a silicon layer formation process to form a silicon layer on the exposed surfaces of the channel pillars, and performing a thermal oxidation process to convert the silicon layer to an oxide layer.

Abstract: A memory cell array includes a bitline encapsulated in a blocking layer within a spacer layer, the bitline extending in a first direction, and a plurality of memory cells aligned in the first direction, each of the plurality of memory cells including a cell transistor having a source electrically connected to the bitline, a drain, a word line, and a channel electrically connected to the source and the drain, and a cell capacitor having a top electrode that is electrically connected to the drain.

Abstract: The present technology includes vertical cell dynamic random-access memory (DRAM) arrays with improved floating body effect. The arrays include one or more bit lines arranged in a first horizontal direction and one or more word lines arranged in a second horizontal direction. The arrays include one or more channels extending in a vertical direction generally orthogonal to the first direction and the second horizontal direction, such that the bit lines intersect with a source/drain region of the plurality of channels, and the word lines intersect with gate regions of the plurality of channels. Arrays include where the source/drain region includes a low bandgap material, where the low bandgap material exhibits a bandgap less than a bandgap of a channel material.

Abstract: Methods of forming memory devices are described. The method comprises forming an oxide layer on a plurality of first layers to fill a plurality of openings in a process cycle including a first sub-cycle and a second sub-cycle. The first sub-cycle includes exposing the film stack to a silicon precursor and ammonia to form a nitride layer on each of the plurality of first layers. The second sub-cycle includes exposing the nitride layer to a plasma to form the oxide layer.

Abstract: Semiconductor processing methods and semiconductor structures are provided with molybdenum-containing features. Methods include etching a substrate to form one or more shallow trench isolations and a plurality of vertically extending channels. Methods include forming one or more molybdenum-containing layers within one or more of the shallow trench isolations. Methods include contacting an exposed surface of the one or more molybdenum-containing layers with a nitrogen-containing precursor, where the contacting nitrides the exposed surface of the one or more molybdenum-containing layers, forming a protective layer over the one or more molybdenum-containing layers.

Abstract: The present disclosure generally relates to dynamic random access memory (DRAM) devices and to semiconductor fabrication for DRAM devices. Certain embodiments disclosed herein provide an integrated processing system and methods for forming CMOS contact, DRAM array bit line contact (BLC), and storage node structures. The integrated processing system and methods enable deposition of contact and storage node layers with reduced contamination and improved quality, thus reducing leakage current and resistance for the final contact and storage node structures.