Patents by Inventor Fredrick Fishburn
Fredrick Fishburn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240038833Abstract: Memory devices and methods of forming memory devices are described. Methods of forming electronic devices are described where carbon is used as the removable mold material for the formation of a DRAM capacitor. A dense, high-temperature (500° C. or greater) PECVD carbon material is used as the removable mold material, e.g., the core material, instead of oxide. The carbon material can be removed by isotropic etching with exposure to radicals of oxygen (O2), nitrogen (N2), hydrogen (H2), ammonia (NH3), and combinations thereof.Type: ApplicationFiled: July 14, 2023Publication date: February 1, 2024Applicant: Applied Materials, Inc.Inventors: Fredrick Fishburn, Tomohiko Kitajima, Qian Fu, Srinivas Guggilla, Hang Yu, Jun Feng, Shih Chung Chen, Lakmal C. Kalutarage, Jayden Potter, Karthik Janakiraman, Deenesh Padhi, Yifeng Zhou, Yufeng Jiang, Sung-Kwan Kang
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SELF-ALIGNED VERTICAL BITLINE FOR THREE-DIMENSIONAL (3D) DYNAMIC RANDOM-ACCESS MEMORY (DRAM) DEVICES
Publication number: 20230380145Abstract: A semiconductor structure includes a plurality of memory levels stacked in a first direction, each of the plurality of memory levels including a semiconductor layer, a word line metal layer, and an interface on a cross section of the semiconductor layer, a spacer between adjacent memory levels of the plurality of memory levels in the first direction, and a bit line in contact with the interface of each of the plurality of memory levels, the bit line extending in the first direction. The bit line comprises metal material, and the interface comprises silicide.Type: ApplicationFiled: May 1, 2023Publication date: November 23, 2023Inventors: Zhijun CHEN, Fredrick FISHBURN, Ying-Bing JIANG, Avgerinos V. GELATOS -
Patent number: 11818877Abstract: Examples herein relate to three-dimensional (3D) dynamic random access memory (DRAM) and corresponding methods. In an example, a film stack is formed on a substrate. The film stack includes multiple unit stacks, each having, sequentially, a first dielectric layer, a semiconductor layer, and a second dielectric layer. A first opening is formed through the film stack. The second dielectric layer is pulled back from the first opening forming a first lateral recess. A gate structure is formed in the first lateral recess and disposed on a portion of the semiconductor layer. A second opening, laterally disposed from where the first opening was formed, is formed through the film stack. The portion of the semiconductor layer is pulled back from the second opening forming a second lateral recess. A capacitor is formed in a region where the second lateral recess was disposed and contacting the portion of the semiconductor layer.Type: GrantFiled: September 27, 2021Date of Patent: November 14, 2023Assignee: Applied Materials, Inc.Inventors: Chang Seok Kang, Tomohiko Kitajima, Sung-Kwan Kang, Fredrick Fishburn, Gill Yong Lee, Nitin K. Ingle
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Publication number: 20230309295Abstract: Provided is a DRAM device having a support layer to hold the bWL features before being filled with the electrode metal. The support layer keeps the structure supported from the top surface but does not prevent the gap fill. A temporary gap-fill material is first deposited in the bWL gaps and then recessed to expose the top edges. A support layer material is then deposited on the structure by plasma enhanced chemical vapor deposition (PECVD). The device is then patterned orthogonal and with pitch greater than the bWL pitch. The temporary gap-fill material is then removed, forming support beams comprising the support material. A metal can then be deposited to fill the bWL gaps under the support beams.Type: ApplicationFiled: March 16, 2023Publication date: September 28, 2023Applicant: Applied Materials, Inc.Inventors: Fredrick Fishburn, Sung-Kwan Kang
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Publication number: 20230307491Abstract: Provided are methods to reduce the thickness of a high-? layer needed in a DRAM capacitor and, thus, allow the cell electrodes to be larger, giving higher cell capacitance. A tantalum nitride (TaN) layer is introduced as a liner in the capacitor hole before a titanium nitride (TiN) electrode layer. The TaN layer converts to a thin layer of tantalum oxide (Ta2O5), which permits a reduction in the high-? layer thickness for the same capacitance versus leakage. Because this Ta2O5 is formed directly on the cell electrode, it ensures a low leakage film exists in the narrowest gaps even before the high-? layer is deposited.Type: ApplicationFiled: March 3, 2023Publication date: September 28, 2023Applicant: Applied Materials, Inc.Inventor: Fredrick Fishburn
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Patent number: 11765889Abstract: Memory devices and methods of forming memory devices are described. Methods of forming electronic devices are described where a spacer is formed around each of the bit line contact pillars, the spacer in contact with the spacer of an adjacent bit line contact pillar. A doped layer is then epitaxially grown on the memory stack and bit line is formed on the memory stack. The bit line is self-aligned with the active region.Type: GrantFiled: April 25, 2022Date of Patent: September 19, 2023Assignee: Applied Materials, Inc.Inventors: Sung-Kwan Kang, Fredrick Fishburn, Abdul Wahab Mohammed, Gill Yong Lee
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Patent number: 11696433Abstract: Memory devices and methods of manufacturing memory devices are provided. Described are devices and methods where 3D pitch multiplication decouples high aspect ratio etch width from cell width, creating small cell active area pitch to allow for small DRAM die size.Type: GrantFiled: May 4, 2021Date of Patent: July 4, 2023Assignee: Applied Materials, Inc.Inventors: Nitin K. Ingle, Fredrick Fishburn
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Publication number: 20230178365Abstract: Semiconductor devices and methods of forming semiconductor devices are described. A method of forming metal silicon nitride films is disclosed. Some embodiments of the disclosure provide a process using ammonia plasma for treating a metal silicide or metal film to form a metal silicon nitride film. The ammonia plasma treatment generates NH* radicals that diffuse through the metal silicide to form a metal silicon nitride film that is substantially free of silicon nitride (SiN). The metal silicon nitride films have improved resistance relative to films deposited by thermal processes or plasma processes with a nitrogen plasma exposure.Type: ApplicationFiled: November 28, 2022Publication date: June 8, 2023Applicant: Applied Materials, Inc.Inventors: Wei Liu, Fredrick Fishburn, Hailing Liu
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Publication number: 20230096309Abstract: Examples herein relate to three-dimensional (3D) dynamic random access memory (DRAM) and corresponding methods. In an example, a film stack is formed on a substrate. The film stack includes multiple unit stacks, each having, sequentially, a first dielectric layer, a semiconductor layer, and a second dielectric layer. A first opening is formed through the film stack. The second dielectric layer is pulled back from the first opening forming a first lateral recess. A gate structure is formed in the first lateral recess and disposed on a portion of the semiconductor layer. A second opening, laterally disposed from where the first opening was formed, is formed through the film stack. The portion of the semiconductor layer is pulled back from the second opening forming a second lateral recess. A capacitor is formed in a region where the second lateral recess was disposed and contacting the portion of the semiconductor layer.Type: ApplicationFiled: September 27, 2021Publication date: March 30, 2023Inventors: Chang Seok KANG, Tomohiko KITAJIMA, Sung-Kwan KANG, Fredrick FISHBURN, Gill Yong LEE, Nitin K. INGLE
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Publication number: 20230055158Abstract: Semiconductor devices and methods of manufacturing the same are described. The methods form a 3D DRAM architecture that includes a semiconductor isolation bridge, eliminating a floating body effect. The method includes forming an epitaxial layer in a deep trench isolation opening and creating a semiconductor isolation bridge between adjacent deep trench isolation openings.Type: ApplicationFiled: August 15, 2022Publication date: February 23, 2023Applicant: Applied Materials, Inc.Inventor: Fredrick Fishburn
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Publication number: 20220352176Abstract: Memory devices and methods of forming memory devices are described. Methods of forming electronic devices are described where a spacer is formed around each of the bit line contact pillars, the spacer in contact with the spacer of an adjacent bit line contact pillar. A doped layer is then epitaxially grown on the memory stack and bit line is formed on the memory stack. The bit line is self-aligned with the active region.Type: ApplicationFiled: April 25, 2022Publication date: November 3, 2022Applicant: Applied Materials, Inc.Inventors: Sung-Kwan Kang, Fredrick Fishburn, Abdul Wahab Mohammed, Gill Yong Lee
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Publication number: 20220336469Abstract: The present disclosure generally relates to dynamic random access memory (DRAM) devices and to semiconductor fabrication for DRAM devices. Certain embodiments disclosed herein provide an integrated processing system and methods for forming CMOS contact, DRAM array bit line contact (BLC), and storage node structures. The integrated processing system and methods enable deposition of contact and storage node layers with reduced contamination and improved quality, thus reducing leakage current and resistance for the final contact and storage node structures.Type: ApplicationFiled: March 7, 2022Publication date: October 20, 2022Inventors: Nicolas Louis BREIL, Fredrick FISHBURN, Byeong Chan LEE
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Publication number: 20220319601Abstract: Described is a memory string including at least one select gate for drain (SGD) transistor and at least one memory transistor in a vertical hole extending through a memory stack on a substrate. The memory stack comprises alternating word lines and dielectric material. There is at least one select-gate-for-drain (SGD) transistor in a first vertical hole extending through the memory stack, the select-gate-for-drain (SGD) transistor comprising a first gate material. At least one memory transistor is in a second vertical hole extending through the memory stack, the at least one memory transistor comprising a second gate material different from the first gate material.Type: ApplicationFiled: March 28, 2022Publication date: October 6, 2022Applicant: Applied Materials, Inc.Inventors: Chang Seok Kang, Tomohiko Kitajima, Gill Yong Lee, Qian Fu, Sung-Kwan Kang, Takehito Koshizawa, Fredrick Fishburn
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Publication number: 20220199627Abstract: Examples herein relate to three-dimensional (3D) dynamic random access memory (DRAM) devices and replacement channel processes for fabricating 3D DRAM devices. In an example, a gate dielectric layer is formed on a sacrificial material, and a gate electrode is formed on the gate dielectric layer. After the gate electrode is formed, the sacrificial material is removed and replaced by a semiconductor material. A channel region of a device (e.g., a transistor) that includes the gate dielectric layer and gate electrode is formed in the semiconductor material. The channel region can be vertical or horizontal with respect to a main surface of a substrate on which the device is formed. A capacitor can be formed, such as before or after the semiconductor material is formed, and is electrically connected to the semiconductor material. The device and the capacitor together can form at least part of a 3D DRAM cell.Type: ApplicationFiled: December 15, 2021Publication date: June 23, 2022Inventors: Fredrick FISHBURN, Arvind KUMAR, Sony VARGHESE
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Publication number: 20210351183Abstract: Memory devices and methods of manufacturing memory devices are provided. Described are devices and methods where 3D pitch multiplication decouples high aspect ratio etch width from cell width, creating small cell active area pitch to allow for small DRAM die size.Type: ApplicationFiled: May 4, 2021Publication date: November 11, 2021Applicant: Applied Materials, Inc.Inventors: Nitin K. Ingle, Fredrick Fishburn
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Publication number: 20050009343Abstract: A method used to form a semiconductor device provides a silicide layer on a plurality of transistor word lines and on a plurality of conductive plugs. In one embodiment, the word lines, one or more sacrificial dielectric layers on the word lines, conductive plugs, and a conductive enhancement layer are formed through the use of a single mask. An in-process semiconductor device which can be formed using one embodiment of the inventive method is also described.Type: ApplicationFiled: July 10, 2003Publication date: January 13, 2005Inventors: Fredrick Fishburn, Terrence McDaniel, Richard Lane