Abstract: A method and array of grouped antenna elements are provided. According to one aspect, a method includes arranging a row of transmit integrated circuits (IC), and a row of receive ICs on an IC chip, and arranging a plurality of IC chips on a panel so that a row of receive circuits on one IC chip is adjacent to a row of receive circuits on an adjacent IC chip.

Abstract: A configurable passive mixer is described herein. According to one exemplary embodiment, a passive mixer for a wireless receiver comprises a plurality of passive mixer cores coupled in parallel with each mixer core configured to receive a same set of radio frequency input signals and a separately driven set of local oscillator input signals. Further, each mixer core is configured to be separately enabled or disabled so that the passive mixer can be selectively configured during operation to convert the same set of radio frequency input signals to a set of downconverted output signals that satisfy a certain performance requirement or performance parameter of the passive mixer.

Abstract: The disclosure concerns controlling circuitry operably connectable to a plurality of constituent analog-to-digital converters (sub-ADCs) of an asynchronous time-interleaved analog-to-digital converter (TI-ADC). The controlling circuitry is configured to maintain a set of a number of sub-ADCs currently available for processing of an input sample, wherein the set is a subset of the plurality. Maintenance of the set is achieved by reception, from each of one or more of the sub-ADCs of the plurality, of an availability signal indicative of availability of the corresponding sub-ADC, and (responsive to the reception of the availability signal) addition of the corresponding sub-ADC to the set. Maintenance of the set is further achieved by (for each new input sample) selection of a sub-ADC of the set for processing of the new input sample, and (responsive to the selection) removal of the selected sub-ADC from the set and causing of the selected sub-ADC to process the new input sample.

Abstract: An analog-to-digital conversion circuit (100) is disclosed. It comprises a switched-capacitor SAR-ADC, (110) arranged to receive an analog input signal (x(t)) and a clock signal, to sample the analog input signal (x(t)), and to generate a sequence (W(n)) of digital output words corresponding to samples of the analog input signal (x(t)), wherein the SAR-ADC (110) is arranged to generate a bit of the digital output word per cycle of the clock signal. It further comprises a clock-signal generator (120) arranged to supply the clock signal to the SAR-ADC (110), and a post-processing unit (140) adapted to receive the sequence (W(n)) of digital output words and generate a sequence of digital output numbers (y(n)), corresponding to the digital output words, based on bit weights assigned to the bits of the digital output words. The bit weights are selected to compensate for a decay of a signal internally in the SAR-ADC (110).

Abstract: An integrated circuit (10, 10a-d) is disclosed, which is configured to be connected to an antenna module (3) having multiple antenna elements (17). The integrated circuit (10, 10a-d) comprises a plurality of communications circuits (50j), each of which is configured to be connected to an antenna element (17) of the antenna module (3). It also comprises a first clock input terminal (551) configured to receive a reference clock signal from outside the integrated circuit (10, 10a-d) and a first clock-distribution network (601) connected between the first clock input terminal (551) and a first subset (651) of the communication circuits (50j). Furthermore, it comprises a second clock input terminal (552) configured to receive a reference clock signal from outside the integrated circuit (10, 10a-d) and a second clock-distribution network (601) connected between the second clock input terminal (552) and a second subset (652) of the communication circuits (50j).

Abstract: The disclosure concerns controlling circuitry operably connectable to a plurality of constituent analog-to-digital converters (sub-ADCs) of an asynchronous time-interleaved analog-to-digital converter (TI-ADC). The controlling circuitry is configured to maintain a set of a number of sub-ADCs currently available for processing of an input sample, wherein the set is a subset of the plurality. Maintenance of the set is achieved by reception, from each of one or more of the sub-ADCs of the plurality, of an availability signal indicative of availability of the corresponding sub-ADC, and (responsive to the reception of the availability signal) addition of the corresponding sub-ADC to the set. Maintenance of the set is further achieved by (for each new input sample) selection of a sub-ADC of the set for processing of the new input sample, and (responsive to the selection) removal of the selected sub-ADC from the set and causing of the selected sub-ADC to process the new input sample.

Abstract: An integrated circuit (10, 10a-d) is disclosed, which is configured to be connected to an antenna module (3) having multiple antenna elements (17). The integrated circuit (10, 10a-d) comprises a plurality of communications circuits (50j), each of which is configured to be connected to an antenna element (17) of the antenna module (3). It also comprises a first clock input terminal (551) configured to receive a reference clock signal from outside the integrated circuit (10, 10a-d) and a first clock-distribution network (601) connected between the first clock input terminal (551) and a first subset (651) of the communication circuits (50j). Furthermore, it comprises a second clock input terminal (552) configured to receive a reference clock signal from outside the integrated circuit (10, 10a-d) and a second clock-distribution network (601) connected between the second clock input terminal (552) and a second subset (652) of the communication circuits (50j).

Abstract: An analog-to-digital conversion circuit (100) is disclosed. It comprises a switched-capacitor SAR-ADC, (110) arranged to receive an analog input signal (x(t)) and a clock signal, to sample the analog input signal (x(t)), and to generate a sequence (W(n)) of digital output words corresponding to samples of the analog input signal (x(t)), wherein the SAR-ADC (110) is arranged to generate a bit of the digital output word per cycle of the clock signal. It further comprises a clock-signal generator (120) arranged to supply the clock signal to the SAR-ADC (110), and a post-processing unit (140) adapted to receive the sequence (W(n)) of digital output words and generate a sequence of digital output numbers (y(n)), corresponding to the digital output words, based on bit weights assigned to the bits of the digital output words. The bit weights are selected to compensate for a decay of a signal internally in the SAR-ADC (110).

Abstract: An integrated circuit (10, 10a-d) is disclosed, which is configured to be connected to an antenna module (3) having multiple antenna elements (17). The integrated circuit (10, 10a-d) comprises a plurality of communications circuits (50j), each of which is configured to be connected to an antenna element (17) of the antenna module (3). It also comprises a first clock input terminal (551) configured to receive a reference clock signal from outside the integrated circuit (10, 10a-d) and a first clock-distribution network (601) connected between the first clock input terminal (551) and a first subset (651) of the communication circuits (50j). Furthermore, it comprises a second clock input terminal (552) configured to receive a reference clock signal from outside the integrated circuit (10, 10a-d) and a second clock-distribution network (601) connected between the second clock input terminal (552) and a second subset (652) of the communication circuits (50j).

Abstract: An integrated circuit (10, 10a-d) is disclosed, which is configured to be connected to an antenna module (3) having multiple antenna elements (17). The integrated circuit (10, 10a-d) comprises a plurality of communications circuits (50j), each of which is configured to be connected to an antenna element (17) of the antenna module (3). It also comprises a first clock input terminal (551) configured to receive a reference clock signal from outside the integrated circuit (10, 10a-d) and a first clock-distribution network (601) connected between the first clock input terminal (551) and a first subset (651) of the communication circuits (50j). Furthermore, it comprises a second clock input terminal (552) configured to receive a reference clock signal from outside the integrated circuit (10, 10a-d) and a second clock-distribution network (601) connected between the second clock input terminal (552) and a second subset (652) of the communication circuits (50j).

Abstract: An integrated circuit (10, 10a-d) is disclosed, which is configured to be connected to an antenna module (3) having multiple antenna elements (17). The integrated circuit (10, 10a-d) comprises a plurality of communications circuits (50j), each of which is configured to be connected to an antenna element (17) of the antenna module (3). It also comprises a first clock input terminal (551) configured to receive a reference clock signal from outside the integrated circuit (10, 10a-d) and a first clock-distribution network (601) connected between the first clock input terminal (551) and a first subset (651) of the communication circuits (50j). Furthermore, it comprises a second clock input terminal (552) configured to receive a reference clock signal from outside the integrated circuit (10, 10a-d) and a second clock-distribution network (601) connected between the second clock input terminal (552) and a second subset (652) of the communication circuits (50j).

Abstract: An integrated circuit (10, 10a-d) is disclosed, which is configured to be connected to an antenna module (3) having multiple antenna elements (17). The integrated circuit (10, 10a-d) comprises a plurality of communications circuits (50j), each of which is configured to be connected to an antenna element (17) of the antenna module (3). It also comprises a first clock input terminal (551) configured to receive a reference clock signal from outside the integrated circuit (10, 10a-d) and a first clock-distribution network (601) connected between the first clock input terminal (551) and a first subset (651) of the communication circuits (50j). Furthermore, it comprises a second clock input terminal (552) configured to receive a reference clock signal from outside the integrated circuit (10, 10a-d) and a second clock-distribution network (601) connected between the second clock input terminal (552) and a second subset (652) of the communication circuits (50j).

Abstract: A configurable passive mixer is described herein. According to one exemplary embodiment, a passive mixer for a wireless receiver comprises a plurality of passive mixer cores coupled in parallel with each mixer core configured to receive a same set of radio frequency input signals and a separately driven set of local oscillator input signals. Further, each mixer core is configured to be separately enabled or disabled so that the passive mixer can be selectively configured during operation to convert the same set of radio frequency input signals to a set of downconverted output signals that satisfy a certain performance requirement or performance parameter of the passive mixer.

Abstract: A mobile communications terminal comprising a radio frequency interface configured to operate at least at a first configuration, and a controller, wherein said controller is configured to determine that a reconfiguration of the radio frequency interface is to be performed, determine a timing of the reconfiguration and reconfigure said radio frequency interface to operate at a second configuration at the determined timing, wherein said controller is configured to determine said timing based on the type of reconfiguration to be made.

Abstract: A configurable passive mixer is described herein. According to one exemplary embodiment, the passive mixer comprises a clock generator, a controller, and a plurality of passive mixer cores connected in parallel. The clock generator comprises a local oscillator drive unit for each passive mixer core. The controller varies an effective transistor size of the passive mixer by separately configuring each of the passive mixer cores to enable/disable each passive mixer core. For example, the controller may selectively enable one or more of the passive mixer cores to vary the effective transistor width of the passive mixer. As the performance requirements and/or the operating communication standard change, the controller may re-configure each passive mixer core.

Abstract: The disclosure pertains to the field of dual access handling. More particularly the disclosure relates to methods of handling more than one connection, each connection corresponding to a respective subscriber identity and connecting a wireless device to a respective wireless network, as well as to a corresponding wireless device and to a computer program. This object is obtained by a method, performed in a wireless device 1, of handling multi access of more than one connection, each connection corresponding to a respective subscriber identity and connecting the wireless device to a respective wireless network. The method comprises detecting S1, for a first connection corresponding to a first subscriber identity, a change in connection properties, and determining S2, for at least one of the other subscriber identities, a set of updated network capabilities, based on the changed connection properties of the first connection.

Abstract: There is provided a method of handling interference caused by inter-modulation in a network node. The method comprises detecting an interference level on an uplink carrier frequency band for stations, and determining whether the interference level indicates probable inter-modulation interference. If the interference level indicates probable inter-modulation interference, the method proceeds with scheduling an uplink transmission grant for at least one of the stations. The uplink transmission grant is valid for a first transmission time interval. The uplink transmission grant is transmitted to the station. A transmit level on the downlink carrier frequency band is assigned at the first transmission time interval such that inter-modulation interference is reduced on the uplink carrier frequency band at the first transmission time interval. An uplink transmission from the station is received at the first transmission time interval.

Abstract: A method of estimation of harmonic distortion level for a radio receiver operative in a cellular communication system enabled to receive signals from transmitters of one or more cells is disclosed. The method comprises measuring, within a bandwidth of operation, a total received signal power; measuring, within the bandwidth of operation, a received signal power of signals received from the one or more cells, respectively; and estimating a level of harmonic receiver distortions by: determining whether a fraction of the total received signal power and a theoretical noise floor is below or above a first threshold; or determining whether a remaining part of the total received signal power, said remaining part not including said fraction, is above or below a second threshold. A such radio receiver, and a computer program for implementing the method are also disclosed.

Abstract: There is provided a method of handling interference caused by inter-modulation in a network node. The method comprises detecting an interference level on an uplink carrier frequency band for stations, and determining whether the interference level indicates probable inter-modulation interference. If the interference level indicates probable inter-modulation interference, the method proceeds with scheduling an uplink transmission grant for at least one of the stations. The uplink transmission grant is valid for a first transmission time interval. The uplink transmission grant is transmitted to the station. A transmit level on the downlink carrier frequency band is assigned at the first transmission time interval such that inter-modulation interference is reduced on the uplink carrier frequency band at the first transmission time interval. An uplink transmission from the station is received at the first transmission time interval.

Abstract: A down-conversion circuit for a receiver circuit is disclosed. It comprises a first mixer arranged to down-convert an RF signal with a first LO signal (LO1), thereby generating a first down-converted signal. It further comprises a second mixer arranged to down-convert the RF signal with a second LO signal (LO2) having the same LO frequency as the first LO signal (LO1), but a different and a second duty cycle, thereby generating a second down-converted signal. The second mixer has an enabled and a disabled mode. The down-conversion circuit also comprises a third mixer arranged to down-convert the RF signal with the second LO signal (LO2), thereby generating a third down-converted signal.