Patents by Inventor Freek Egbert Van Straten

Freek Egbert Van Straten has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11929310
    Abstract: Radio frequency (RF) packages containing substrates having coefficient of thermal expansion (CTE) matched mount pads are disclosed, as are methods for fabricating RF packages and substrates. In embodiments, the RF package contains a high thermal performance substrate including a metallic base structure, which has a frontside facing a first RF power die and a first die attach region on the frontside of the base structure. A first CTE matched mount pad is bonded to the metallic base structure and covers the first die attach region. The first CTE mount pad has a CTE greater than the CTE of RF power die and less than the CTE of the metallic base structure. An electrically-conductive bonding material attaches the RF power die to the first CTE matched mount pad, while RF circuitry integrated into first RF power die is electrically coupled to the metallic base structure through the mount pad.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: March 12, 2024
    Assignee: NXP USA, Inc.
    Inventors: Lu Li, Lakshminarayan Viswanathan, Freek Egbert van Straten
  • Patent number: 11842957
    Abstract: An amplifier module includes a module substrate with a mounting surface, a signal conducting layer, a ground layer, and a ground terminal pad at the mounting surface. A thermal dissipation structure extends through the module substrate. A ground contact of a power transistor die is coupled to a surface of the thermal dissipation structure. Encapsulant material covers the mounting surface of the module substrate and the power transistor die, and a surface of the encapsulant material defines a contact surface of the amplifier module. A ground terminal is embedded within the encapsulant material. The ground terminal has a proximal end coupled to the ground terminal pad, and a distal end exposed at the contact surface. The ground terminal is electrically coupled to the ground contact of the power transistor die through the ground terminal pad, the ground layer of the module substrate, and the thermal dissipation structure.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: December 12, 2023
    Assignee: NXP USA, Inc.
    Inventors: Jeffrey Kevin Jones, Kevin Kim, Freek Egbert van Straten, Ibrahim Khalil
  • Publication number: 20230230924
    Abstract: A substrate is described with a thermal dissipation structure sintered to thermal vias. In one example, a microelectronic module includes a recess between first and second substrate surfaces. One or more thermal vias extend between the first substrate surface and the interior recess surface, wherein each of the thermal vias has an interior end exposed at the interior recess surface. A sintered metal layer is in the recess and in physical contact with the interior end of the thermal vias and a thermal dissipation structure is in the recess over the sintered metal layer. The thermal dissipation structure is attached to the substrate within the recess by the sintered metal layer, and the thermal dissipation structure is thermally coupled to the thermal vias through the sintered metal layer.
    Type: Application
    Filed: February 28, 2023
    Publication date: July 20, 2023
    Inventors: Lu Li, Lakshminarayan Viswanathan, Freek Egbert van Straten
  • Publication number: 20230187325
    Abstract: Radio frequency (RF) packages containing substrates having coefficient of thermal expansion (CTE) matched mount pads are disclosed, as are methods for fabricating RF packages and substrates. In embodiments, the RF package contains a high thermal performance substrate including a metallic base structure, which has a frontside facing a first RF power die and a first die attach region on the frontside of the base structure. A first CTE matched mount pad is bonded to the metallic base structure and covers the first die attach region. The first CTE mount pad has a CTE greater than the CTE of RF power die and less than the CTE of the metallic base structure. An electrically-conductive bonding material attaches the RF power die to the first CTE matched mount pad, while RF circuitry integrated into first RF power die is electrically coupled to the metallic base structure through the mount pad.
    Type: Application
    Filed: December 9, 2021
    Publication date: June 15, 2023
    Inventors: Lu Li, Lakshminarayan Viswanathan, Freek Egbert van Straten
  • Patent number: 11621228
    Abstract: A substrate is described with a thermal dissipation structure sintered to thermal vias. In one example, a microelectronic module includes a recess between first and second substrate surfaces. One or more thermal vias extend between the first substrate surface and the interior recess surface, wherein each of the thermal vias has an interior end exposed at the interior recess surface. A sintered metal layer is in the recess and in physical contact with the interior end of the thermal vias and a thermal dissipation structure is in the recess over the sintered metal layer. The thermal dissipation structure is attached to the substrate within the recess by the sintered metal layer, and the thermal dissipation structure is thermally coupled to the thermal vias through the sintered metal layer.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: April 4, 2023
    Assignee: NXP USA, Inc.
    Inventors: Lu Li, Lakshminarayan Viswanathan, Freek Egbert van Straten
  • Publication number: 20220384307
    Abstract: A thermal interface structure for transferring heat from an electronic component to a system heat sink includes a stack of one or more layers of a stiff thermal interface material and one or more layers of a compliant thermal interface material stacked on and connected to the one or more layers of the compliant thermal interface material. In some embodiments, the thermal interface structure also may include one or more layers of a shape memory alloy and/or a collapsible encasement.
    Type: Application
    Filed: June 1, 2021
    Publication date: December 1, 2022
    Inventors: Lu Li, Sharan Kishore, Freek Egbert van Straten, Lakshminarayan Viswanathan
  • Publication number: 20220208670
    Abstract: An amplifier module includes a module substrate with a mounting surface, a signal conducting layer, a ground layer, and a ground terminal pad at the mounting surface. A thermal dissipation structure extends through the module substrate. A ground contact of a power transistor die is coupled to a surface of the thermal dissipation structure. Encapsulant material covers the mounting surface of the module substrate and the power transistor die, and a surface of the encapsulant material defines a contact surface of the amplifier module. A ground terminal is embedded within the encapsulant material. The ground terminal has a proximal end coupled to the ground terminal pad, and a distal end exposed at the contact surface. The ground terminal is electrically coupled to the ground contact of the power transistor die through the ground terminal pad, the ground layer of the module substrate, and the thermal dissipation structure.
    Type: Application
    Filed: December 29, 2020
    Publication date: June 30, 2022
    Inventors: Jeffrey Kevin Jones, Kevin Kim, Freek Egbert van Straten, Ibrahim Khalil
  • Publication number: 20220068817
    Abstract: A substrate is described with a thermal dissipation structure sintered to thermal vias. In one example, a microelectronic module includes a recess between first and second substrate surfaces. One or more thermal vias extend between the first substrate surface and the interior recess surface, wherein each of the thermal vias has an interior end exposed at the interior recess surface. A sintered metal layer is in the recess and in physical contact with the interior end of the thermal vias and a thermal dissipation structure is in the recess over the sintered metal layer. The thermal dissipation structure is attached to the substrate within the recess by the sintered metal layer, and the thermal dissipation structure is thermally coupled to the thermal vias through the sintered metal layer.
    Type: Application
    Filed: August 31, 2020
    Publication date: March 3, 2022
    Inventors: Lu LI, Lakshminarayan VISWANATHAN, Freek Egbert van Straten
  • Patent number: 9911628
    Abstract: For so called film assisted molding (FAM) device processing techniques there is provided lead frame for a semiconductor device, comprising a base portion and a connection lead, said base portion arranged for mounting a semiconductor die, said connection lead comprising a horizontal portion for external connection and an angled portion for connection to said semiconductor die, wherein the angled portion has a positive angle with respect to the base portion. The connection lead may comprise a recessed portion.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: March 6, 2018
    Assignee: Ampleon Netherlands B.V.
    Inventors: Freek Egbert van Straten, Jeremy Joy Montalbo Incomio, Albertus Reijs
  • Publication number: 20170110343
    Abstract: For so called film assisted moulding (FAM) device processing techniques there is provided lead frame for a semiconductor device, comprising a base portion and a connection lead, said base portion arranged for mounting a semiconductor die, said connection lead comprising a horizontal portion for external connection and an angled portion for connection to said semiconductor die, wherein the angled portion has a positive angle with respect to the base portion. The connection lead may comprise a recessed portion.
    Type: Application
    Filed: December 28, 2016
    Publication date: April 20, 2017
    Inventors: Freek Egbert van Straten, Jeremy Joy Montalbo Incomio, Albertus Reijs
  • Patent number: 9570323
    Abstract: For so called film assisted moulding (FAM) device processing techniques there is provided lead frame for a semiconductor device, comprising a base portion and a connection lead, said base portion arranged for mounting a semiconductor die, said connection lead comprising a horizontal portion for external connection and an angled portion for connection to said semiconductor die, wherein the angled portion has a positive angle with respect to the base portion. The connection lead may comprise a recessed portion.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: February 14, 2017
    Assignee: Ampleon Netherlands B.V.
    Inventors: Freek Egbert van Straten, Jeremy Joy Montalbo Incomio, Albertus Reijs
  • Patent number: 9190350
    Abstract: For so called film assisted moulding (FAM) device processing techniques there is provided lead frame for a semiconductor device, comprising a base portion and a connection lead, said base portion arranged for mounting a semiconductor die, said connection lead comprising a horizontal portion for external connection and an angled portion for connection to said semiconductor die, wherein the angled portion has a positive angle with respect to the base portion. The connection lead may comprise a recessed portion.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: November 17, 2015
    Assignee: NXP B.V.
    Inventors: Freek Egbert van Straten, Jeremy Joy Montalbo Incomio, Albertus Reijs
  • Patent number: 9184469
    Abstract: A battery comprises a carrier foil, with solid state battery elements spaced along the foil and mounted on opposite sides of the foil in pairs, with the battery elements of a pair mounted at the same position along the foil. The carrier foil is folded to define a meander pattern with battery element pairs that are adjacent each other along the foil arranged back to back.
    Type: Grant
    Filed: November 2, 2011
    Date of Patent: November 10, 2015
    Assignee: NXP B.V.
    Inventors: Friso Jacobus Jedema, Willem Frederik Adrianus Besling, Freddy Roozeboom, René Wilhelmus Johannes Maria van den Boomen, Freek Egbert van Straten
  • Publication number: 20150084174
    Abstract: For so called film assisted moulding (FAM) device processing techniques there is provided lead frame for a semiconductor device, comprising a base portion and a connection lead, said base portion arranged for mounting a semiconductor die, said connection lead comprising a horizontal portion for external connection and an angled portion for connection to said semiconductor die, wherein the angled portion has a positive angle with respect to the base portion. The connection lead may comprise a recessed portion.
    Type: Application
    Filed: September 4, 2014
    Publication date: March 26, 2015
    Inventors: Freek Egbert van Straten, Jeremy Joy Montalbo Incomio, Albertus Reijs
  • Publication number: 20150084175
    Abstract: For so called film assisted moulding (FAM) device processing techniques there is provided lead frame for a semiconductor device, comprising a base portion and a connection lead, said base portion arranged for mounting a semiconductor die, said connection lead comprising a horizontal portion for external connection and an angled portion for connection to said semiconductor die, wherein the angled portion has a positive angle with respect to the base portion. The connection lead may comprise a recessed portion.
    Type: Application
    Filed: September 5, 2014
    Publication date: March 26, 2015
    Inventors: Freek Egbert van Straten, Jeremy Joy Montalbo Incomio, Albertus Reijs
  • Patent number: 8854277
    Abstract: A millimeter-wave radio antenna module (600) comprising: an antenna substrate (603) having an antenna (602) provided on a face thereof; and a semiconductor die (601) comprising a wireless system IC, the die mounted on a face of the antenna substrate and configured to provide a signal to the antenna, wherein a ball grid array (605) is formed on a face of the antenna substrate for mounting the antenna module to a circuit board, the ball grid array being configured to define an air dielectric gap (606) between the antenna and the circuit board.
    Type: Grant
    Filed: November 16, 2009
    Date of Patent: October 7, 2014
    Assignee: NXP, B.V.
    Inventors: Antonius Johannes Matheus De Graauw, Freek Egbert Van Straten
  • Publication number: 20120116189
    Abstract: A battery comprises a carrier foil, with solid state battery elements spaced along the foil and mounted on opposite sides of the foil in pairs, with the battery elements of a pair mounted at the same position along the foil. The carrier foil is folded to define a meander pattern with battery element pairs that are adjacent each other along the foil arranged back to back.
    Type: Application
    Filed: November 2, 2011
    Publication date: May 10, 2012
    Applicant: NXP B.V.
    Inventors: Friso Jacobus Jedema, Willem Frederik Adrianus Besling, Freddy Roozeboom, René Wilhelmus Johannes Maria van den Boomen, Freek Egbert van Straten
  • Publication number: 20110285606
    Abstract: A millimetre-wave radio antenna module (600) comprising: an antenna substrate (603) having an antenna (602) provided on a face thereof; and a semiconductor die (601) comprising a wireless system IC, the die mounted on a face of the antenna substrate and configured to provide a signal to the antenna, wherein a ball grid array (605) is formed on a face of the antenna substrate for mounting the antenna module to a circuit board, the ball grid array being configured to define an air dielectric gap (606) between the antenna and the circuit board.
    Type: Application
    Filed: November 16, 2009
    Publication date: November 24, 2011
    Applicant: NXP B.V.
    Inventors: Antonius Johannes Matheus De Graauw, Freek Egbert Van Straten
  • Patent number: 7394994
    Abstract: An optical receiver circuit comprising an optical converter circuit (38), comprising a photodiode and converting optical power into electrical power, a sensor circuit for deriving a control voltage VCONTR as a characteristic value of the electrical power output by the optical converter circuit (38); and an attenuator circuit (44) having a variable attenuation, the attenuation being controlled by the characteristic value of the electrical power output by the sensor circuit so as to obtain a constant output signal level of the optical receiver circuit. An output circuit is also provided and comprises a matching network (46), an amplifier stage (48) and an output transformer (50).
    Type: Grant
    Filed: July 1, 2003
    Date of Patent: July 1, 2008
    Assignee: NXP B.V.
    Inventors: Joost Maarten Zitzmann, Freek Egbert Van Straten