Patents by Inventor Freeman Yingquan Zhong

Freeman Yingquan Zhong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9014252
    Abstract: A channel equalization scheme is provided. A linear equalizer using a continuous-time linear equalization and a decision feedback equalizer using a discrete-time decision feedback equalization are integrated together from a hybrid receiver equalizer. The continuous-time linear equalization scheme and the discrete-time decision feedback equalization scheme are blended using a joint adaptation algorithm to form an equalization scheme for inter-symbol interference cancellation in the hybrid receiver equalizer. The hybrid receiver equalizer controls crosstalk while maintaining signal bandwidth and linearity of a signal by the high-order high frequency roll-off of the linear equalizer used. Using this configuration, the hybrid receiver equalizer eliminates the need for adaptive bandwidth controller used in conventional low-pass receiver equalization schemes. The hybrid receiver equalizer can be used in receivers for dual-speed simultaneous transmission on the same physical link.
    Type: Grant
    Filed: December 6, 2006
    Date of Patent: April 21, 2015
    Assignee: LSI Corporation
    Inventors: Yikui (Jen) Dong, Cathy Ye Liu, Freeman Yingquan Zhong
  • Patent number: 7961817
    Abstract: In a receiver, an AC-coupling solution uses a fully integrated circuit for simultaneously providing both baseline wander compensation and common-mode voltage generation. Usefully, an integrated capacitor is placed between the receiver input pin and the input buffer, and a high resistive impedance element is connected to the internal high-speed data node after the capacitor. An on-chip voltage generation and correction circuit is connected to the other side of the impedance element to generate a common-mode voltage, and to provide dynamic, fine adjustment for the received data voltage level. The voltage correction circuit is controlled by the feedback of data detected by the clock and data recovery unit (CDRU) of the receiver. The feedback data passes through a weighting element, wherein the amount of feedback gain is adjustable to provide a summing weight and thereby achieve a desired BLW compensation.
    Type: Grant
    Filed: December 6, 2006
    Date of Patent: June 14, 2011
    Assignee: LSI Corporation
    Inventors: Yikui (Jen) Dong, Cathy Ye Liu, Freeman Yingquan Zhong, Shao Ming Hsu
  • Publication number: 20080069191
    Abstract: A system and a method for channel equalization are provided. A linear equalizer using a continuous-time linear equalization and a decision feedback equalizer using a discrete-time decision feedback equalization are integrated together from a hybrid receiver equalizer. The continuous-time linear equalization scheme and the discrete-time decision feedback equalization scheme are blended using a joint adaptation algorithm to form an equalization scheme for inter-symbol interference cancellation in the hybrid receiver equalizer. The hybrid receiver equalizer controls crosstalk while maintaining signal bandwidth and linearity of a signal by the high-order high frequency roll-off of the linear equalizer used. Using this configuration, the hybrid receiver equalizer eliminates the need for adaptive bandwidth controller used in conventional low-pass receiver equalization schemes. The hybrid receiver equalizer can be used in receivers for dual-speed simultaneous transmission on the same physical link.
    Type: Application
    Filed: December 6, 2006
    Publication date: March 20, 2008
    Inventors: Yikui (Jen) Dong, Cathy Ye Liu, Freeman Yingquan Zhong
  • Publication number: 20080063091
    Abstract: In a receiver, an AC-coupling solution uses a fully integrated circuit for simultaneously providing both baseline wander compensation and common-mode voltage generation. Usefully, an integrated capacitor is placed between the receiver input pin and the input buffer, and a high resistive impedance element is connected to the internal high-speed data node after the capacitor. An on-chip voltage generation and correction circuit is connected to the other side of the impedance element to generate a common-mode voltage, and to provide dynamic, fine adjustment for the received data voltage level. The voltage correction circuit is controlled by the feedback of data detected by the clock and data recovery unit (CDRU) of the receiver. The feedback data passes through a weighting element, wherein the amount of feedback gain is adjustable to provide a summing weight and thereby achieve a desired BLW compensation.
    Type: Application
    Filed: December 6, 2006
    Publication date: March 13, 2008
    Inventors: Yikui (Jen) Dong, Cathy Ye Liu, Freeman Yingquan Zhong, Shao Ming Hsu