Patents by Inventor Freerk Van Rijs
Freerk Van Rijs has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240106396Abstract: The present invention relates to a push-pull amplifying unit and a Doherty amplifier. The push-pull amplifying unit comprises a first amplifier, a second amplifier, a first shunt inductor, and a second shunt inductor. The first and second shunt inductors have mutually connected second terminals and are inductively coupled to increase the impedance between the first output and the virtual ground and the impedance between the second output and the virtual ground at a fundamental frequency of a signal to be amplified by the push-pull amplifying unit relative to those impedances in the absence of said inductive coupling, and to decrease the impedance between the first output and the virtual ground and the impedance between the second output and the virtual ground at a second harmonic frequency of the signal to be amplified relative to those impedances in the absence of said inductive coupling.Type: ApplicationFiled: February 4, 2022Publication date: March 28, 2024Inventors: Mohammad Reza BEIKMIRZA, Seyed Morteza ALAVI, Leonardus Cornelis Nicolaas DE VREEDE, Freerk VAN RIJS, Radjindrepersad GAJADHARSING
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Publication number: 20230139209Abstract: An RF transmitter (1) having a gate-segmented power output stage (2) and a digital driver (5). The gate-segmented power output stage (2) includes a field-effect transistor with a plurality of gate fingers (32) and drain fingers (31) that define a gate periphery. The field-effect transistor comprises a plurality of power output stage segments (3) that each correspond to a respective part of the gate periphery, and that each have a respective power output stage segment input (4). The digital driver (5) has control outputs (6) which are connected to corresponding ones of the respective power output stage segment inputs (4), and is configured for individually switching each of the power output stage segments (3) between an on mode and a cut-off mode in dependence of one or more input signals to obtain a modulated RF carrier signal at an output (7) of the gate-segmented power output stage (2).Type: ApplicationFiled: February 5, 2021Publication date: May 4, 2023Applicant: Technische Universiteit DelftInventors: Leonardus Cornelis Nicolaas de Vreede, Seyed Morteza Alavi, Robert Jan Bootsman, Mohammad Reza Beikmirza, Dieuwert Peter Nicolaas Mul, Rob Heeres, Freerk van Rijs
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Patent number: 10763227Abstract: The present disclosure relates to a packaged radiofrequency (RF) power amplifier. The present disclosure further relates to a semiconductor die that is used in such a power amplifier and to an electronic device or system that comprises the semiconductor die and/or power amplifier. According to the disclosure, the semiconductor die comprises a second drain bond assembly arranged spaced apart from the first drain bond assembly and electrically connected thereto, wherein the second drain bond assembly is arranged closer to the input side of the semiconductor die than the first drain bond assembly. The RF power amplifier comprises a first plurality of bondwires which extend between the first drain bond assembly and the output lead, and a second plurality of bondwires which extend from the second drain bond assembly to a first terminal of a grounded capacitor.Type: GrantFiled: December 12, 2018Date of Patent: September 1, 2020Assignee: Ampleon Netherlands B.V.Inventors: Rob Mathijs Heeres, Freerk van Rijs
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Patent number: 10453810Abstract: The present disclosure relates to a radio frequency (RF) power transistor package. It further relates to a mobile telecommunications base station comprising such an RF power transistor package, and to an integrated passive die suitable for use in an RF power amplifier package. In example embodiments, an in-package impedance network is used that is connected to an output of the RF power transistor arranged inside the package. This network comprises a first inductive element having a first and second terminal, the first terminal being electrically connected to the output of the RF transistor, a resonance unit electrically connected to the second terminal of the first inductive element, and a second capacitive element electrically connected in between the resonance unit and ground, where the first capacitive element is arranged in series with the second capacitive element.Type: GrantFiled: January 29, 2019Date of Patent: October 22, 2019Assignee: Ampleon Netherlands B.V.Inventors: Johannes Adrianus Maria De Boet, Freerk Van Rijs, Iordan Konstantinov Sveshtarov
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Publication number: 20190181106Abstract: The present disclosure relates to a packaged radiofrequency (RF) power amplifier. The present disclosure further relates to a semiconductor die that is used in such a power amplifier and to an electronic device or system that comprises the semiconductor die and/or power amplifier. According to the disclosure, the semiconductor die comprises a second drain bond assembly arranged spaced apart from the first drain bond assembly and electrically connected thereto, wherein the second drain bond assembly is arranged closer to the input side of the semiconductor die than the first drain bond assembly. The RF power amplifier comprises a first plurality of bondwires which extend between the first drain bond assembly and the output lead, and a second plurality of bondwires which extend from the second drain bond assembly to a first terminal of a grounded capacitor.Type: ApplicationFiled: December 12, 2018Publication date: June 13, 2019Inventors: Rob Mathijs Heeres, Freerk van Rijs
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Publication number: 20190172804Abstract: The present disclosure relates to a radio frequency (RF) power transistor package. It further relates to a mobile telecommunications base station comprising such an RF power transistor package, and to an integrated passive die suitable for use in an RF power amplifier package. In example embodiments, an in-package impedance network is used that is connected to an output of the RF power transistor arranged inside the package. This network comprises a first inductive element having a first and second terminal, the first terminal being electrically connected to the output of the RF transistor, a resonance unit electrically connected to the second terminal of the first inductive element, and a second capacitive element electrically connected in between the resonance unit and ground, where the first capacitive element is arranged in series with the second capacitive element.Type: ApplicationFiled: January 29, 2019Publication date: June 6, 2019Applicant: Ampleon Netherlands B.V.Inventors: Johannes Adrianus Maria De Boet, Freerk Van Rijs, Iordan Konstantinov Sveshtarov
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Patent number: 10242960Abstract: The present disclosure relates to a radio frequency (RF) power transistor package. It further relates to a mobile telecommunications base station comprising such an RF power transistor package, and to an integrated passive die suitable for use in an RF power amplifier package. In example embodiments, an in-package impedance network is used that is connected to an output of the RF power transistor arranged inside the package. This network comprises a first inductive element having a first and second terminal, the first terminal being electrically connected to the output of the RF transistor, a resonance unit electrically connected to the second terminal of the first inductive element, and a second capacitive element electrically connected in between the resonance unit and ground, where the first capacitive element is arranged in series with the second capacitive element.Type: GrantFiled: July 20, 2017Date of Patent: March 26, 2019Assignee: Ampleon Netherlands B.V.Inventors: Johannes Adrianus Maria De Boet, Freerk Van Rijs, Iordan Konstantinov Sveshtarov
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Publication number: 20180026000Abstract: The present disclosure relates to a radio frequency (RF) power transistor package. It further relates to a mobile telecommunications base station comprising such an RF power transistor package, and to an integrated passive die suitable for use in an RF power amplifier package. In example embodiments, an in-package impedance network is used that is connected to an output of the RF power transistor arranged inside the package. This network comprises a first inductive element having a first and second terminal, the first terminal being electrically connected to the output of the RF transistor, a resonance unit electrically connected to the second terminal of the first inductive element, and a second capacitive element electrically connected in between the resonance unit and ground, where the first capacitive element is arranged in series with the second capacitive element.Type: ApplicationFiled: July 20, 2017Publication date: January 25, 2018Applicant: Ampleon Netherlands B.V.Inventors: Johannes Adrianus Maria De Boet, Freerk Van Rijs, Iordan Konstantinov Sveshtarov
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Patent number: 8416023Abstract: System and method for compensating for changes in an output impedance of a power amplifier uses an impedance compensating circuit with an impedance inverter coupled to the power amplifier. The impedance inverter of the impedance compensating circuit is configured such that an output impedance of the impedance inverter is proportional to the inverse of the output impedance of the power amplifier to compensate for changes in the output impedance of the power amplifier.Type: GrantFiled: June 8, 2010Date of Patent: April 9, 2013Assignee: NXP B.V.Inventors: Freerk van Rijs, Alexander Otto Harm
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Publication number: 20110298535Abstract: System and method for compensating for changes in an output impedance of a power amplifier uses an impedance compensating circuit with an impedance inverter coupled to the power amplifier. The impedance inverter of the impedance compensating circuit is configured such that an output impedance of the impedance inverter is proportional to the inverse of the output impedance of the power amplifier to compensate for changes in the output impedance of the power amplifier.Type: ApplicationFiled: June 8, 2010Publication date: December 8, 2011Applicant: NXP B.V.Inventors: Freerk Van Rijs, Alexander Otto Harm
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Patent number: 7989879Abstract: The LDMOS transistor (1) of the invention comprises a source region (3), a channel region (4), a drain extension region (7) and a gate electrode (10). The LDMOS transistor (1) further comprises a first gate oxide layer (8) and a second gate oxide layer (9), which is thicker than the first gate oxide layer (8). The first gate oxide layer (8) at least extends over a first portion of the channel region (4), which is adjacent to the source region (3). The second gate oxide layer (9) extends over a region where a local maximum (A, B) of the electric field (E) generates hot carriers thereby reducing the impact of the hot carriers and reducing the Idq-degradation. In another embodiment the second gate oxide layer (9) extends over a second portion of the channel region (4), which mutually connects the drain extension region (7) and the first portion of the channel region (4), thereby improving the linear efficiency of the LDMOS transistor (1).Type: GrantFiled: July 10, 2006Date of Patent: August 2, 2011Assignee: NXP B.V.Inventors: Freerk Van Rijs, Stephan J. C. H. Theeuwen, Petra C. A. Hammes
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Publication number: 20090218622Abstract: The LDMOS transistor (1) of the invention comprises a source region (3), a channel region (4), a drain extension region (7) and a gate electrode (10). The LDMOS transistor (1) further comprises a first gate oxide layer (8) and a second gate oxide layer (9), which is thicker than the first gate oxide layer (8). The first gate oxide layer (8) at least extends over a first portion of the channel region (4), which is adjacent to the source region (3). The second gate oxide layer (9) extends over a region where a local maximum (A, B) of the electric field (E) generates hot carriers thereby reducing the impact of the hot carriers and reducing the Idq-degradation. In another embodiment the second gate oxide layer (9) extends over a second portion of the channel region (4), which mutually connects the drain extension region (7) and the first portion of the channel region (4), thereby improving the linear efficiency of the LDMOS transistor (1).Type: ApplicationFiled: July 10, 2006Publication date: September 3, 2009Applicant: NXP B.V.Inventors: Freerk Van Rijs, Stephan J., C., H. Theeuwen, Petra C., A. Hammes
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Patent number: 7521768Abstract: The LDMOS transistor (99) of the invention is provided with a stepped shield structure (50) and/or with a first (25) and a second (26) drain extension region having a higher dopant concentration than the second drain extension region, and being covered by the shield.Type: GrantFiled: August 24, 2004Date of Patent: April 21, 2009Assignee: NXP B.V.Inventors: Stephan Jo Cecile Henri Theeuwen, Freerk Van Rijs, Petra Christina Anna Hammes, Ivo Bernhard Pouwel, Hendrikus Ferdinand Franciscus Jos
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Publication number: 20080237705Abstract: The LDMOS transistor (1) of the invention comprises a substrate (2), a gate electrode (10), a substrate contact region (11), a source region (3), a channel region (4) and a drain region (5), which drain region (5) comprises a drain contact region (6) and drain extension region (7). The drain contact region (6) is electrically connected to a top metal layer (23), which extends over the drain extension region (7), with a distance (723) between the top metal layer (23) and the drain extension region (7) that is larger than 2?m. This way the area of the drain contact region (6) may be reduced and the RF power output efficiency of the LDMOS transistor (1) increased. In another embodiment the source region (3) is electrically connected to the substrate contact region (11) via a suicide layer (32) instead of a first metal layer (21), thereby reducing the capacitive coupling between the source region (3) and the drain region (5) and hence increasing the RF power output efficiency of the LDMOS transistor (1) further.Type: ApplicationFiled: August 2, 2006Publication date: October 2, 2008Applicant: NXP B.V.Inventors: Stephan Jo Cecile Henri Theeuwen, Freerk Van Rijs, Petra C.A. Hammes
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Publication number: 20070007591Abstract: The LDMOS transistor (99) of the invention is provided with a stepped shield structure (50) and/or with a first (25) and a second (26) drain extension region having a higher dopant concentration than the second drain extension region, and being covered by the shield.Type: ApplicationFiled: August 24, 2004Publication date: January 11, 2007Inventors: Stephan jo Cecile Theeuwen, Freerk Van Rijs, Petra Christina Hammes, Ivo Pouwel, Henrikus Ferdinand Jos
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Patent number: 6917077Abstract: A semiconductor arrangement including: a substrate having a substrate layer (13) with an upper and lower surface, the substrate layer (13) being of a first conductivity type; a first buried layer (12) in the substrate, extending along said lower surface below a first portion of said upper surface of said substrate layer (13), and a second buried layer (12) in the substrate, extending along said lower surface below a second portion of said upper surface of said substrate layer (13); a first diffusion (26) in said first portion of said substrate layer (13), being of a second conductivity type opposite to said first conductivity type and having a first distance to said first buried layer (12) for defining a first breakdown voltage between said first diffusion (26) and said first buried layer (12); a second diffusion (45) in said second portion of said substrate layer (13), being of said second conductivity type and having a second distance to said second buried layer (12) for defining a second breakdown voltaType: GrantFiled: October 5, 2001Date of Patent: July 12, 2005Assignee: Koninklijke Philips Electronics N.V.Inventors: Petrus Hubertus Cornelis Magnee, Freerk Van Rijs, Hendrik Gezienus Albert Huizing
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Patent number: 6593628Abstract: The invention relates to an essentially discrete semiconductor device comprising a semiconductor body (10) having a first, preferably bipolar, transistor (T1) with a first region (1) forming a collector (1) of T1, and a second, preferably also bipolar, transistor (T2) with a second region (2) forming a collector (2) of T2, which transistors (T1, T2) are in a cascode configuration wherein the collector (1) of T1is connected to the emitter (4) of T2. Such a device cannot suitably be used in a base station for mobile communication. According to the invention, the first region (1) and the second region (2) are positioned next to each other within a semiconductor region (5), a part of which situated below the first region (1) is provided with a higher doping concentration at the location of T1. In this way, T1 has a low collector-emitter breakdown voltage and a high cutoff frequency, whereas for T2 said voltage and frequency are, respectively, high(er) and low(er).Type: GrantFiled: March 28, 2001Date of Patent: July 15, 2003Assignee: Koninklijke Philips Electronics N.V.Inventors: Ronald Dekker, Henricus Godefridus Rafael Maas, Jan Willem Slotboom, Freerk Van Rijs
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Publication number: 20030030127Abstract: The bipolar transistor comprises a collector region (1) of a semiconductor material with a first doping type, an emitter region (2) with a first doping type, and a base region (3) of a semiconductor material with a second doping type, opposite to the first doping type, which base region is arranged between the emitter region (2) and the collector region (1), and a semiconductor area (4) extending between the collector region (1) and the base region (3).Type: ApplicationFiled: August 2, 2002Publication date: February 13, 2003Inventors: Hendrik Gezienus Albert Huizing, Jan Willem Slotboom, Igor Lyuboshenko, Johan Hendrik Klootwijk, Freerk Van Rijs, Joost Melai
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Patent number: 6437420Abstract: The invention relates to a semiconductor device (100) with a semiconductor body (10) comprising at least one semiconductor element (H) with an active area (A) and a coil (20) coupled to said element (H). The coil (20) and a further coil (21) jointly form a transformer (F). The semiconductor body (10) is secured to a carrier plate (30) which comprises an electrically insulating material and is covered with a conductor track (21). According to the invention, the further coil (21) is positioned on the carrier plate (30) and is formed by the conductor track (21) and electrically separated from the coil (20). In this way, a-device (100) is obtained which is easier to manufacture than the known device. Moreover, the communication between the element (H) and the outside world does not involve an electrical coupling and hence, for example, bonding wires, are not necessary. The invention is particularly advantageous for a (discrete) bipolar transistor, which can suitably be used for surface mounting.Type: GrantFiled: July 10, 2000Date of Patent: August 20, 2002Assignee: Koninklijke Philips Electronics N. V.Inventors: Freerk Van Rijs, Ronald Dekker
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Publication number: 20020096713Abstract: The present invention relates to semi-conductor device comprising:Type: ApplicationFiled: January 22, 2002Publication date: July 25, 2002Applicant: Koninklijke Philips Electronics N.V.Inventors: Petrus Hubertus Cornelis Magnee, Hendrik Gezienus Albert Huizing, Freerk Van Rijs