Abstract: A system for blending includes a memory device, cache, cache controller, and a graphics processing device. The graphics processing device performs blending of a plurality of source images into a single destination image. The graphics processing device performs a method including, for each tile position in the plurality of source images, requesting tiles for the tile position form each source image, blending the tiles individually with a destination tile and overwriting the destination tile in the cache with the result of the blending after each individual blending. The destination tile may be written to memory after each source tile for the each tile position has been blended with the destination tile, such as in response to a cache controller determining that the destination tile is a least recently used (LRU) entry in the cache.

Abstract: A system for blending is disclosed including a memory device, cache, cache controller, and a graphics processing device. The graphics processing device performs blending of a plurality of source images into a single destination image. The graphics processing device performs a method including, for each tile position in the plurality of source images, requesting tiles for the tile position form each source image, blending the tiles individually with a destination tile and overwriting the destination tile in the cache with the result of the blending after each individual blending. The destination tile may be written to memory after each source tile for the each tile position has been blended with the destination tile, such as in response to a cache controller determining that the destination tile is a least recently used (LRU) entry in the cache.

Abstract: A method and apparatus for hardware rotation is described. In one embodiment, the invention is an apparatus. The apparatus includes a direct access address translation component. The apparatus also includes a frame buffer coupled to the direct access address translation component. The apparatus further includes a 2D coordinate translation component. The apparatus also includes a 2D engine coupled to the 2D coordinate translation component and to the frame buffer. The apparatus further includes a 3D engine. The apparatus also include a 3D coordinate translation component coupled to the 3D engine and the frame buffer. As will be appreciated, further embodiments of the invention are within the spirit and scope of the claimed invention, and the specific details of a specific embodiment as described need not be present in all embodiments of the invention.

Abstract: An apparatus and method for rasterizing a primitive in a graphics system is disclosed in one example of the invention as including scanning a first row of tiles, one tile at a time, starting from a first point and scanning in a first direction. Immediately after scanning the first row of tiles, the method includes moving from the first point to a second point in an orthogonal direction relative to the first row. Immediately after moving from the first point to the second point, the method includes scanning a second row of tiles, one tile at a time, starting from the second point and scanning in the first direction. By scanning rows in the same direction immediately prior to and after moving from one row to another, cache utilization is improved.

Abstract: An apparatus and method for rasterizing a primitive in a graphics system is disclosed in one example of the invention as including scanning a first row of tiles, one tile at a time, starting from a first point and scanning in a first direction. Immediately after scanning the first row of tiles, the method includes moving from the first point to a second point in an orthogonal direction relative to the first row. Immediately after moving from the first point to the second point, the method includes scanning a second row of tiles, one tile at a time, starting from the second point and scanning in the first direction. By scanning rows in the same direction immediately prior to and after moving from one row to another, cache utilization is improved.

Abstract: An apparatus and method to dynamically regulate system bandwidth in a graphics system includes receiving vertex data from an application by way of an application programming interface. The rate that the vertex data is received from the application is then determined. In the event the rate is greater than a selected threshold, the graphics system is configured to operate in immediate mode, wherein vertex data is rendered immediately upon reception. In the event the rate is less than the selected threshold, the graphics system is configured to operate in retained mode, wherein vertex data is stored prior to being rendered. The apparatus and method switches between each of the modes on-the-fly in a manner that is transparent to the application.

Abstract: A hierarchical tile-based rasterization method is disclosed. The inventive rasterization algorithm rasterizes pixels in hierarchical rectangles or blocks. The method includes: walking a plurality of tiles of pixels and determining if each tile is valid; breaking each valid tile into a plurality of subtiles and determining if each subtile is valid; breaking each valid subtile into a plurality of quads and determining if each quad is valid; and rendering pixels for each valid quad. These hierarchical levels of block validations are performed in parallel. The inventive rasterization algorithm is further implemented in hardware for better performance.

Abstract: A system to facilitate virtual page translation. An embodiment of the system includes a processing device, a front end unit, and address translation logic. The processing device is configured to process data of a current block of data. The front end unit is coupled to the processing device. The front end unit is configured to access the current block of data in an electronic memory device and to send the current block of data to the processor for processing. The address translation logic is coupled to the front end unit and the electronic memory device. The address translation logic is configured to pre-fetch a virtual address translation for a predicted virtual address based on a virtual address of the current block of data. Embodiments of the system increase address translation performance of computer systems including graphic rendering operations.

Abstract: An apparatus and method for rasterizing a primitive in a graphics system is disclosed in one example of the invention as including scanning a first row of tiles, one tile at a time, starting from a first point and scanning in a first direction. Immediately after scanning the first row of tiles, the method includes moving from the first point to a second point in an orthogonal direction relative to the first row. Immediately after moving from the first point to the second point, the method includes scanning a second row of tiles, one tile at a time, starting from the second point and scanning in the first direction. By scanning rows in the same direction immediately prior to and after moving from one row to another, cache utilization is improved.

Abstract: A distributed clipping scheme is provided, view frustum culling is distributed in several places in a graphics processing pipeline to simplify hardware implementation and improve performance. In general, many 3D objects are outside viewing frustum. In one embodiment, clipping is performed on these objects with a simple algorithm in the PA module, such as near Z clipping, trivial rejection and trivial acceptance. In one embodiment, the SE and RA modules perform the rest of clipping, such as X, Y and far Z clipping. In one embodiment, the SE module performs clipping by way of computing a initial point of rasterization. In one embodiment, the RA module performs clipping by way of conducting the rendering step of the rasterization process. This approach distributes the complexity in the graphics processing pipeline and makes the design simpler and faster, therefore design complexity, cost and performance may all be improved in hardware implementation.

Abstract: A method and apparatus for hardware rotation is described. In one embodiment, the invention is an apparatus. The apparatus includes a direct access address translation component. The apparatus also includes a frame buffer coupled to the direct access address translation component. The apparatus further includes a 2D coordinate translation component. The apparatus also includes a 2D engine coupled to the 2D coordinate translation component and to the frame buffer. The apparatus further includes a 3D engine. The apparatus also include a 3D coordinate translation component coupled to the 3D engine and the frame buffer. As will be appreciated, further embodiments of the invention are within the spirit and scope of the claimed invention, and the specific details of a specific embodiment as described need not be present in all embodiments of the invention.

Abstract: A distributed clipping scheme is provided, view frustum culling is distributed in several places in a graphics processing pipeline to simplify hardware implementation and improve performance. In general, many 3D objects are outside viewing frustum. In one embodiment, clipping is performed on these objects with a simple algorithm in the PA module, such as near Z clipping, trivial rejection and trivial acceptance. In one embodiment, the SE and RA modules perform the rest of clipping, such as X, Y and far Z clipping. In one embodiment, the SE module performs clipping by way of computing a initial point of rasterization. In one embodiment, the RA module performs clipping by way of conducting the rendering step of the rasterization process. This approach distributes the complexity in the graphics processing pipeline and makes the design simpler and faster, therefore design complexity, cost and performance may all be improved in hardware implementation.

Abstract: A method and apparatus for hardware rotation is described. In one embodiment, the invention is an apparatus. The apparatus includes a direct access address translation component. The apparatus also includes a frame buffer coupled to the direct access address translation component. The apparatus further includes a 2D coordinate translation component. The apparatus also includes a 2D engine coupled to the 2D coordinate translation component and to the frame buffer. The apparatus further includes a 3D engine. The apparatus also include a 3D coordinate translation component coupled to the 3D engine and the frame buffer. As will be appreciated, further embodiments of the invention are within the spirit and scope of the claimed invention, and the specific details of a specific embodiment as described need not be present in all embodiments of the invention.

Abstract: An apparatus and method to dynamically regulate system bandwidth in a graphics system includes receiving vertex data from an application by way of an application programming interface. The rate that the vertex data is received from the application is then determined. In the event the rate is greater than a selected threshold, the graphics system is configured to operate in immediate mode, wherein vertex data is rendered immediately upon reception. In the event the rate is less than the selected threshold, the graphics system is configured to operate in retained mode, wherein vertex data is stored prior to being rendered. The apparatus and method switches between each of the modes on-the-fly in a manner that is transparent to the application.

Abstract: An apparatus and method for rasterizing a primitive in a graphics system is disclosed in one example of the invention as including scanning a first row of tiles, one tile at a time, starting from a first point and scanning in a first direction. Immediately after scanning the first row of tiles, the method includes moving from the first point to a second point in an orthogonal direction relative to the first row. Immediately after moving from the first point to the second point, the method includes scanning a second row of tiles, one tile at a time, starting from the second point and scanning in the first direction. By scanning rows in the same direction immediately prior to and after moving from one row to another, cache utilization is improved.

Abstract: A system to facilitate virtual page translation. An embodiment of the system includes a processing device, a front end unit, and address translation logic. The processing device is configured to process data of a current block of data. The front end unit is coupled to the processing device. The front end unit is configured to access the current block of data in an electronic memory device and to send the current block of data to the processor for processing. The address translation logic is coupled to the front end unit and the electronic memory device. The address translation logic is configured to pre-fetch a virtual address translation for a predicted virtual address based on a virtual address of the current block of data. Embodiments of the system increase address translation performance of computer systems including graphic rendering operations.

Abstract: A method and apparatus for Font Emulation are disclosed. In one embodiment, the method comprises stripping a first portion from a first font to emulate a second font upon request for such a second font. In an alternative embodiment, the apparatus comprises a processor and a memory, the processor stripping a first portion from a first font to emulate a second font. The method and apparatus may further include stripping a second portion from a first font, and such may be performed by the processor. Alternatively, the method may include copying a first font into memory.

Abstract: The invention in one embodiment is a method of managing power in a graphics controller. The method includes receiving a change indication related to a system power supply. The method also includes adjusting a first clock or adjusting a set of clocks including a first clock. The method further includes adjusting a controller power supply voltage.

Abstract: According to one aspect of the invention, there is provided a method for accessing data in a memory to be performed. The method includes receiving a request to read a file stored in the memory, the memory having a fragmented array of files across a single partition. The method also includes building a look up table (LUT) for the memory. The method also includes storing the LUT in the processor. The method also includes accessing the LUT in the processor to create an index table which specifies a plurality of addresses for the file. The method further includes storing the index table in the memory.

Abstract: In one embodiment, the invention is a method. The method includes receiving a request at a primary device to play an audio file, where the primary device is in a power saving state. The method also includes accessing a storage location on the primary device. The method further includes locating a play list which has a record of the audio file. Moreover, the method includes choosing the audio file from the play list and playing the audio file.