Abstract: A device includes a direct memory access (DMA) controller comprising DMA channels, a bridge circuit configured to couple the DMA channels to memory channels coupled to respective memory modules, and a local memory unit. The DMA controller is configured to transfer tensor data between the local memory unit and the memory modules via the DMA channels and the memory channels using concurrent data transactions, the tensor data is stored and addressed as parts of a single tensor in the local memory unit, and the tensor data is interleaved onto the memory modules and is stored and addressed as sub-tensors in respective memory modules.

Abstract: A device includes a memory storing a first lookup table of entries each comprising a starting index value and a number of samples corresponding to a respective segment of a function and a second lookup table of entries each comprising a respective sampled mantissa from the function. An interpolation logic circuit retrieves from the first lookup table a starting index value and a number of samples corresponding to a segment of the function corresponding to an input mantissa from an input floating-point element, retrieves from the second lookup table a first sampled mantissa and a second sampled mantissa based on the starting index value and the number of samples retrieved from the first lookup table and the input mantissa, and interpolates an output mantissa.

Abstract: A radio frequency receiver with dual band reception and dual analog-to-digital converters (ADCs) can be configured to operate in a single channel mode or a dual channel mode to receive a single RF input channel or two RF input channels at the same or different frequency bands. In the single channel mode, the dual ADCs can be used to improve the performance of the receiver for the single input signal or the dual ADCs can be configured for reduced power consumption. In the dual channel mode, the dual ADCs operate on the individual RF input signals to realize dual band reception. In one embodiment, the receiver is configured for asymmetric dual band reception to receive a wideband input signal on a first input signal path and a narrow band input signal on a second input signal path.

Abstract: A method in a television receiver receiving interlaced analog modulated television signals includes: detecting an inactive video period in the television signal between two successive video display fields; generating a synchronization signal indicative of the detected inactive video period; and in response to the synchronization signal, performing measurement and adjustment operations on analog circuitry of the television receiver. In another embodiment, a method in a television receiver receiving interlaced analog modulated television signals includes: detecting an inactive video period between two successive video display fields using a not-fully-demodulated intermediate frequency (IF) signal; and generating a synchronization signal indicative of the detected inactive video period.

Abstract: A method in a mixed-signal system to prevent overlapping of clock edges of one or more digital clock signals and clock edges of one or more analog clock signals where the digital clock signals and the analog clock signals are digitally controlled includes generating one or more timing window pulses that are centered around the clock edges of one of the digital clock signals or the analog clock signals; combining the timing window pulses to generate a gating signal, the gating signal having an active logical level at each of the timing window pulses; and applying the gating signal to gate or delay clock edges of the other one of the digital clock signals or the analog clock signals.

Abstract: A mixed-signal radio frequency receiver implements multiple spur avoidance modes to reduce or remove spurs or digital noise injection into the received channel to enhance the receiver performance. The multiple spur avoidance modes are reconfigurable to allow a single mode or multiple modes to be selected for use depending on the application. One or more spur avoidance modes can be selected to enhance the performance of the receiver or the modes can be selected to reduce power consumption. The same spur avoidance circuit is used to support all of the spur avoidance modes by reconfiguring the circuit for each mode or each combination of modes. In another embodiment, a clock masking scheme is applied to align analog and digital clock edges to separate digital activities from sensitive analog activities.

Abstract: A digital-to-analog converter (DAC) implements a hybrid conversion architecture where the input digital data is oversampled and a flash converter is used to convert the M most significant bits (MSBs) of the oversampled data while a sigma-delta (?-?) converter is used to convert the remaining least significant bits (LSBs) of the oversampled data. In one embodiment, a merged flash converter is used to convert the M MSBs and the digital bit stream generated by the sigma-delta converter.

Abstract: A method in a television receiver receiving interlaced analog modulated television signals includes: detecting an inactive video period in the television signal between two successive video display fields; generating a synchronization signal indicative of the detected inactive video period; and in response to the synchronization signal, performing measurement and adjustment operations on analog circuitry of the television receiver. In another embodiment, a method in a television receiver receiving interlaced analog modulated television signals includes: detecting an inactive video period between two successive video display fields using a not-fully-demodulated intermediate frequency (IF) signal; and generating a synchronization signal indicative of the detected inactive video period.

Abstract: A digital-to-analog converter (DAC) implements a hybrid conversion architecture where the input digital data is oversampled and a flash converter is used to convert the M most significant bits (MSBs) of the oversampled data while a sigma-delta (?-?) converter is used to convert the remaining least significant bits (LSBs) of the oversampled data. In one embodiment, a merged flash converter is used to convert the M MSBs and the digital bit stream generated by the sigma-delta converter.

Abstract: A digital video formatting system operates to format an analog format video signal to within a desired amplitude range using an adaptive filtering scheme which implements flat gain scaling, frequency-dependent gain scaling and adaptive offset correction. The adaptive filtering scheme selects a frequency-independent flat gain scaling mode or a frequency-dependent gain scaling mode based on the characteristics of the active video signal. The filtered video signal is fed back to an adaptive weight computation block to update the offset correction value, the filter coefficients and the mode selection signal.

Abstract: A method in a mixed-signal system to prevent overlapping of clock edges of one or more digital clock signals and clock edges of one or more analog clock signals where the digital clock signals and the analog clock signals are digitally controlled includes generating one or more timing window pulses that are centered around the clock edges of one of the digital clock signals or the analog clock signals; combining the timing window pulses to generate a gating signal, the gating signal having an active logical level at each of the timing window pulses; and applying the gating signal to gate or delay clock edges of the other one of the digital clock signals or the analog clock signals.

Abstract: A mixed-signal radio frequency receiver implements multiple spur avoidance modes to reduce or remove spurs or digital noise injection into the received channel to enhance the receiver performance. The multiple spur avoidance modes are reconfigurable to allow a single mode or multiple modes to be selected for use depending on the application. One or more spur avoidance modes can be selected to enhance the performance of the receiver or the modes can be selected to reduce power consumption. The same spur avoidance circuit is used to support all of the spur avoidance modes by reconfiguring the circuit for each mode or each combination of modes. In another embodiment, a clock masking scheme is applied to align analog and digital clock edges to separate digital activities from sensitive analog activities.

Abstract: A radio frequency receiver with dual band reception and dual analog-to-digital converters (ADCs) can be configured to operate in a single channel mode or a dual channel mode to receive a single RF input channel or two RF input channels at the same or different frequency bands. In the single channel mode, the dual ADCs can be used to improve the performance of the receiver for the single input signal or the dual ADCs can be configured for reduced power consumption. In the dual channel mode, the dual ADCs operate on the individual RF input signals to realize dual band reception. In one embodiment, the receiver is configured for asymmetric dual band reception to receive a wideband input signal on a first input signal path and a narrow band input signal on a second input signal path.

Abstract: A digital video formatting system operates to format an analog format video signal to within a desired amplitude range using an adaptive filtering scheme which implements flat gain scaling, frequency-dependent gain scaling and adaptive offset correction. The adaptive filtering scheme selects a frequency-independent flat gain scaling mode or a frequency-dependent gain scaling mode based on the characteristics of the active video signal. The filtered video signal is fed back to an adaptive weight computation block to update the offset correction value, the filter coefficients and the mode selection signal.

Abstract: A television receiver includes a frequency conversion circuit, an analog-to-digital converter, a signal processor, and a signal output circuit. The frequency conversion circuit receives an input RF signal in one of several television signal formats and converts the input RF signal to an intermediate frequency signal. The analog-to-digital converter samples the intermediate frequency signal and generates a digital representation thereof. The signal processor processes the digital representation of the intermediate frequency signal in accordance with the television signal format of the input RF signal and generates digital output signals indicative of information encoded in the input RF signal. Finally, the signal output circuit receives the digital output signals from the signal processor and provides one or more output signals corresponding to the digital output signals.

Abstract: A television receiver includes a frequency conversion circuit, an analog-to-digital converter, a signal processor, and a signal output circuit. The frequency conversion circuit receives an input RF signal in one of several television signal formats and converts the input RF signal to an intermediate frequency signal. The analog-to-digital converter samples the intermediate frequency signal and generates a digital representation thereof. The signal processor processes the digital representation of the intermediate frequency signal in accordance with the television signal format of the input RF signal and generates digital output signals indicative of information encoded in the input RF signal. Finally, the signal output circuit receives the digital output signals from the signal processor and provides one or more output signals corresponding to the digital output signals.