Abstract: A power semiconductor device includes a semiconductor wafer having a first main side surface and a second main side surface. The semiconductor wafer includes a first semiconductor layer having a first conductivity type and a plurality of columnar or plate-shaped first semiconductor regions extending in the first semiconductor layer between the first main side surface and the second main side surface in a vertical direction perpendicular to the first main side surface and the second main side surface. The first semiconductor regions have a second conductivity type, which is different from the first conductivity type. Therein, the first semiconductor is a layer of hexagonal silicon carbide. The first semiconductor regions are regions of 3C polytype silicon carbide.

Abstract: A high power semiconductor device with a floating field ring termination includes a wafer, wherein a plurality of floating field rings is formed in an edge termination region adjacent to a first main side surface of the wafer. At least in the termination region a drift layer, in which the floating field rings are formed, includes a surface layer and a bulk layer wherein the surface layer is formed adjacent to the first main side surface to separate the bulk layer from the first main side surface and has an average doping concentration which is less than 50% of the minimum doping concentration of the bulk layer. The drift layer includes a plurality of enhanced doping regions, wherein each one of the enhanced doping regions is in direct contact with a corresponding one of the floating field rings at least on a lateral side of this floating field ring, which faces towards the active region.

Abstract: In a power semiconductor device of the application a total number n of floating field rings (10_1 to 10_n) formed in a termination area is at least 10. For any integer i in a range from i=2 to i=n, a ring-to-ring separation di,i?i between an i-th floating field ring and a directly adjacent (i?1)-th floating field ring, when counting the floating field rings (10_1 to 10_n) along a straight line starting from a main pn-junction and extending in a lateral direction away from the main pn-junction, is given by the following formula: di,i?1=d1,0+?j=1j=i?1 ?j for i=2 to n, wherein d1,0 is a distance between the innermost floating field ring (10_1) closest to the main pn-junction and the main pn-junction, and wherein: ?zone1?0.05·?zone2<?j<?zone1+0.05·?zone2 for j=1 to I?2, 2·?zone2<|?j|<10·?zone2. for j=I?1, 0.95·?zone2<?j<1.05·?zone2 for j=I to n?1, ?zone2>0.1 ?m, and ??zone2/2<?zone1<?zone2/2, wherein I is an integer, for which 3?l?n/2.

Abstract: A power semiconductor device includes a semiconductor wafer having a first main side surface and a second main side surface. The semiconductor wafer includes a first semiconductor layer having a first conductivity type and a plurality of columnar or plate-shaped first semiconductor regions extending in the first semiconductor layer between the first main side surface and the second main side surface in a vertical direction perpendicular to the first main side surface and the second main side surface. The first semiconductor regions have a second conductivity type, which is different from the first conductivity type. Therein, the first semiconductor is a layer of hexagonal silicon carbide. The first semiconductor regions are regions of 3C polytype silicon carbide.

Abstract: In a power semiconductor device of the application a total number n of floating field rings (10_1 to 10_n) formed in a termination area is at least 10. For any integer i in a range from i=2 to i=n, a ring-to-ring separation di,1?i between an i-th floating field ring and a directly adjacent (i?1)-th floating field ring, when counting the floating field rings (10_1 to 10_n) along a straight line starting from a main pn-junction and extending in a lateral direction away from the main pn-junction, is given by the following formula: di,i?1=d1,0+?j=1j=i?1 ?j for i=2 to n, wherein d1,0 is a distance between the innermost floating field ring (10_1) closest to the main pn-junction and the main pn-junction, and wherein: ?zone1?0.05·?zone2<?j<?zone1+0.05·?zone2 for j=1 to I-2, 2·?zone2<zone2<Aj<Azonel +0.05 A zone2 <|?j|<10·?zone2. for j=I?1, 0.95·?zone2<?j<1.05·?zone2 for j=I to n?1, ?zone2<0.1 ?m, and ??zone2/2 <?zone1<?zone2/2 , wherein I is an integer, for which 3?l?n/2.

Abstract: A high power semiconductor device with a floating field ring termination includes a wafer, wherein a plurality of floating field rings is formed in an edge termination region adjacent to a first main side surface of the wafer. At least in the termination region a drift layer, in which the floating field rings are formed, includes a surface layer and a bulk layer wherein the surface layer is formed adjacent to the first main side surface to separate the bulk layer from the first main side surface and has an average doping concentration which is less than 50% of the minimum doping concentration of the bulk layer. The drift layer includes a plurality of enhanced doping regions, wherein each one of the enhanced doping regions is in direct contact with a corresponding one of the floating field rings at least on a lateral side of this floating field ring, which faces towards the active region.

Abstract: A junction barrier Schottky rectifier with first and second drift layer sections, wherein a peak net doping concentration of the first section is at least two times lower than a minimum net doping concentration of the second section. For each emitter region the first section includes a layer which is in contact with the respective emitter region to form a pn-junction between the first section and the respective emitter region, wherein the thickness of this layer in a direction perpendicular to the interface between the first section and the respective emitter region is at least 0.1 ?m. The JBS rectifier has a transition from unipolar to bipolar conduction mode at a lower forward bias due to lowering of electrostatic forces otherwise impairing the transport of electrons toward the emitter regions under forward bias conditions, and with reduced snap-back phenomenon.

Abstract: A power semiconductor device is provided comprising: a collector electrode, a collector layer of a second conductivity type, a drift layer of a first conductivity type, a base layer of the second conductivity type, a first insulating layer having an opening, an emitter layer of the first conductivity type, the emitter layer contacts the base layer and separated from the drift layer by one of the first insulating layer or the base layer, a body layer of the second conductivity type arranged laterally to the emitter layer and separated from the base layer by the first insulating layer and the emitter layer, a source region of the first conductivity type separated from the emitter layer by the body layer, an emitter electrode contacted by the source region.

Abstract: A junction barrier Schottky rectifier with first and second drift layer sections, wherein a peak net doping concentration of the first section is at least two times lower than a minimum net doping concentration of the second section. For each emitter region the first section includes a layer which is in contact with the respective emitter region to form a pn-junction between the first section and the respective emitter region, wherein the thickness of this layer in a direction perpendicular to the interface between the first section and the respective emitter region is at least 0.1 ?m. The JBS rectifier has a transition from unipolar to bipolar conduction mode at a lower forward bias due to lowering of electrostatic forces otherwise impairing the transport of electrons toward the emitter regions under forward bias conditions, and with reduced snap-back phenomenon.

Abstract: An insulated gate bipolar device is disclosed which can include layers of different conductivity types between an emitter electrode on an emitter side and a collector electrode on a collector side in the following order: a source region of a first conductivity type, a base layer of a second conductivity type, which contacts the emitter electrode in a contact area, an enhancement layer of the first conductivity type, a floating compensation layer of the second conductivity type having a compensation layer thickness tp, a drift layer of the first conductivity type having lower doping concentration than the enhancement layer and a collector layer of the second conductivity type.

Abstract: An insulated gate bipolar device is disclosed which can include layers of different conductivity types between an emitter electrode on an emitter side and a collector electrode on a collector side in the following order: a source region of a first conductivity type, a base layer of a second conductivity type, which contacts the emitter electrode in a contact area, an enhancement layer of the first conductivity type, a floating compensation layer of the second conductivity type having a compensation layer thickness tp, a drift layer of the first conductivity type having lower doping concentration than the enhancement layer and a collector layer of the second conductivity type.

Abstract: A bipolar power semiconductor device is provided with an emitter electrode on an emitter side and a collector electrode on a collector side. The device has a trench gate electrode and a structure with a plurality of layers of different conductivity types in the following order: at least one n doped source region, a p doped base layer, which surrounds the at least one source region, an n doped enhancement layer, a p doped additional well layer, an additional n doped enhancement layer, an additional p doped well layer, an n doped drift layer and a p doped collector layer. The trench gate electrode has a gate bottom, which is located closer to the collector side than the additional enhancement layer bottom.

Abstract: A bipolar power semiconductor device is provided with an emitter electrode on an emitter side and a collector electrode on a collector side. The device has a trench gate electrode and a structure with a plurality of layers of different conductivity types in the following order: at least one n doped source region, a p doped base layer, which surrounds the at least one source region, an n doped enhancement layer, a p doped additional well layer, an additional n doped enhancement layer, an additional p doped well layer, an n doped drift layer and a p doped collector layer. The trench gate electrode has a gate bottom, which is located closer to the collector side than the additional enhancement layer bottom.

Abstract: An IGBT is specified which can be produced in a simple manner yet can be turned on homogeneously. For this purpose, gate fingers are dispensed with and the gate current in the IGBT-Chip is forwarded, proceeding from the gate terminal, directly via the polysilicon layers of the gate electrodes to the IGBT standard cells.

Abstract: A GTO is specified which, starting from the anode-side main surface (2), comprises an anode emitter (6), a barrier layer (11), an n-base (7), a p-base (8) and a cathode emitter (9). The anode emitter (6) is designed as a transparent emitter and has anode short-circuits (10). By virtue of the combination of the barrier layer, the transparent anode emitter and the anode short-circuits, a GTO is obtained which can be operated at high switching frequencies, the substrate thickness of which can be reduced and which nevertheless exhibits no increase in the switching losses.

Abstract: In a MOS-controlled turn-off thyristor (MCT), a conventional integral cell with a combined emitter and short-circuiting function is replaced by a separate DMOS cell (D) and emitter cell (E). The DMOS cell (D) contains a five-layer sequence of cathode short-circuit region (18), first channel region (19), second base layer (7), first base layer (8) and emitter layer (9). The emitter cell (E) contains a four-layer sequence of first emitter region (20), second base layer (7), first base layer (8) and emitter layer (9). This basic structure produces a component which is easy to produce and is distinguished by a high reverse-blocking capability.

Abstract: A power semiconductor component is specified which provides for a significant reduction in the thickness of the semiconductor substrate (1) whilst at the same time optimizing the switching losses. A transparent emitter (6) and a stop layer (7) are arranged to provide a thin semiconductor and optimized switching losses. The means can be used both in semiconductor switches such as IGBT, MCT or GTO and in diodes.

Abstract: In the case of a controllable power semiconductor component, which comprises at least one planar, essentially rectangular power semiconductor chip (13), which power semiconductor chip (13) has on its top side a large-area metallization layer (14) for the large-area electrical connection to a metal mating element (17, 19), and also a separate small-area connection region for the gate connection in the form of a gate pad (16), a simplified form of the metal mating element (17, 19) and adjustment thereof are achieved by virtue of the fact that the gate pad (16) is arranged in a corner of the power semiconductor chip (13).

Abstract: A diode (1) is specified which has electron injection means on the anode-side principal surface (3). After the reverse-current peak has been traversed, said means inject electrons into the anode emitter. This compensates for holes and the danger of a dynamic field overshoot, which may result in an avalanche breakdown, is reduced. The electron injection means preferably comprise an n-channel MOS cell. High voltages and high dI/dt values can be safely handled with a diode according to the invention. A diode in accordance with the invention is preferably used as freewheeling diode in a converter circuit arrangement.

Abstract: In an MOS-controlled power semiconductor component having a multiplicity of cathode cells, the surface area proportion of the cathode cells relative to the total component surface area is selected at between 0.1% and 10% in the case of circular cell geometry and between 0.4% and 40% in the case of strip-shaped cell geometry. As a result of this, the susceptibility to oscillation caused by small inductances can be reduced. (FIG.