Abstract: A binary encoded phase modulated signal (biphase signal) is demodulated by determining the period of time (T) elapsing between each two successive jumps in the level of the biphase signal; providing a clock frequency (B) approximately corresponding to the bit rate of the biphase signal with the aid of a clock generator; comparing the clock duration (1/B) of the clock frequency with the period of time (T) between each two jumps in level; and, with the aid of a sample and hold circuit controlled by the clock frequency (B), always ascertaining the logical value of the biphase signal and emitting a signal corresponding to the logical value whenever, immediately prior to a bit period, twice in succession, a value between 1/4 and 3/4 of 1/B is ascertained for the period of time (T), or a value between 3/4 and 5/4 of 1/B is ascertained for the period of time (T).