Abstract: For the purpose of connecting a plurality of independent processor units to a single port of a main memory, the processor units are connected in series over individual interface controls, whereby the interfaces are expanded in comparison to the port interface without the interface conditions for the port being changed. The interface controls operate in reciprocal dependency on one another so that the memory access request arising within the processor unit chain becomes effective in individual succession by way of a reciprocal inhibiting without address control, whereby variable connector controls in the interface lines determine the transmission path of both directions between the main memory and the respectively active processor depending upon status signals which, among other things, are influenced by interface signals. Termination of a write operation and clear down of a completed connection occurs by way of an internal interface line of the chain circuit.