Abstract: A circuit arrangement for driving a capcitive load comprises a control circuit (1), whose output is the collector of an output transistor (2). The collector is coupled through the gatesource path of a junction field effect transistor (5) and a resistor (6) connected parallel thereto to the capacitive load (8). The drain connection of the J-FET is connected to the supply voltage (Ub). The circuit permits rapid switching of the load while maintaining the current consumption relatively low.

Abstract: A circuit arrangement for producing a direct voltage from a sinusoidal input voltage comprising a filter for suppressing interference voltages, a rectifier, a switched mode power supply part and a pulse generator. The pulse generator produces from the rectified input signal switching pulses for the switched mode power supply part. The frequency of these pulses is varied so that it is a minimum at the maximum value of the rectified input voltage and is a maximum at the minimum value and is varied between the extreme values so that the second derivative of the frequency with respect to time is always zero or negative. A switching pulse is terminated when a signal proportional to the output current of the rectifier exceeds the difference between a signal proportional to the rectified input voltage and an integrated signal proportional to the output current of the rectifier.