Abstract: An electrically programmable memory cell contains a source-drain series arrangement of a field-effect select transistor arrangement and a complementary pair of memory transistors arranged between a first bit line and a second bit line. The pair of memory transistors comprises a common electrically floating storage gate and a common control gate which is connected to one programming line. Each of the electrodes of the select transistors is connected to the row selecting line associated therewith. The drain regions which are connected to one another, are lead to a read line. The memory cell according to the invention permits reading without requiring any significant DC power, and programming by using the complete programming voltage as available.

Abstract: A memory cell includes a selection transistor and a memory transistor formed as insulated gate field effect transistors. The transistors are formed on a substrate with a channel for the selection transistor coupled to a channel for the memory transistor. A layer of oxide overlies both transistors. The channels are formed between a programming line and a reading line formed in the substrate. A thin film window in the oxide overlies a region of the programming line. An insulated, floating gate is formed overlying the window and the channel of the memory transistor. A gate electrode overlies the floating gate and the channel of the selection transistor.

Abstract: A semiconductor memory cell includes a source-drain series connection of several memory transistors each comprising electrically floating gates and being of the depletion type, with a selection transistor being disposed between a first bit line and a second bit line. The memory cell remains programmable as long as one of the series-arranged memory transistors has an injector oxide free from defects. The memory transistors having an injector oxide damaged by a breakdown are not programmable but do not affect the programmability of the respective semiconductor memory cell.

Abstract: An integrated voltage divider is provided having a series arrangement of resistors. Each tapping point between resistors is connected to the output by a switching circuit comprised of transistors. A selection circuit comprising an open circuit decoder and a short circuit decoder is connected to individual gates of the switching transistors to selectively operate such switching transistors.

Abstract: The control power input of a power stage designed in the form of a CMOS inverter can be considerably reduced according to the invention in that, with the aid of a driver stage splitting the digital input signal, each of the two gate electrodes of the two field-effect transistors of the power stage, are simultaneously but separately controlled by each time one driver signal of the same polarity, thus each time raising the source-gate voltage of one of the two field-effect transistors above its threshold voltage value.

Abstract: In order to obtain a low as possible generator internal resistance, a first inverter (IV1) is arranged between the first and the third potential (U1, U3), and the switching section of a second inverter (IV2) is connected to the zero point of the circuit and to the output of the first inverter (IV1) which is modified in such a way that between the switching sections of its two transistors (T21, T22) there is inserted an intermediate transistor (MT). The point connecting the switching sections of the intermediate transistor (MT) and of the other transistor (T22) of the second inverter (IV2) is the output of the selection circuit and is arranged, via the switching section of an additional transistor (ZT) to the second potential (U2).

Abstract: A memory access and control circuit is described for use with a non-volatile memory matrix utilizing insulated gate field effect transistors. Two one out of n selector circuits which are complementary in operation and which are formed from transistors of opposite conductivity type are formed on an integrated circuit and transistors of one conductivity type are formed in insulating islands in the substrate.

Abstract: In a circuit for selecting a random number (N) of potentials (Ui . . . ), which is integrated in accordance with the complementary insulated-gate field-effect transistor technique, one transmission gate (G . . . ) is associated with each potential, with the switching section of the gate lying between the potential (Ui . . . ) and the output (U), and the two control inputs of the respective transmission gate (G . . . ) are connected either directly or via a respectively associated inverter (I . . . ) to the corresponding output of a CMOS-1-ex-n-decoder. This decoder may consist of a 1-ex-n-open-circuit-decoder (SD) and of a 1-ex-n-short-circuit decoder (KD) whose address inputs are connected in pairs to one another and whose like outputs (1 . . . 8) are connected to one another. The open-circuit decoder (SD) consists of transistors (TP) of the one channel conductivity type, and the short-circuit decoder (KD) consists of transistors (TN) of the other channel conductivity type.

Abstract: The invention discloses a monolithic integrated reference voltage source consisting of a source-drain series arrangement of a depletion-type n-channel MOSFET connected to the supply potential and of an enhancement-type n-channel MOSFET connected to a reference potential. The gate electrode of the depletion-type transistor is connected to the reference potential, while the reference voltage is taken off the point connecting the two transistors, to which point the gate electrode of the enhancement-type transistor is connected. When certain manufacturing requirements are observed as regards the gate oxide layer thickness, the substrate doping and the ratio r of the width-to-length ratio (W=width and L=length of the conducting channel), the circuit displays a very small temperature dependence of the reference voltage and a small surface requirement.

Abstract: A non-volatile programmable integrated semi-conductor cell comprises a semiconductive substrate of one conductivity type, a reading insulated-gate field effect transistor partially incorporated in said substrate and having an insulated gate at the active surface of the substrate, and a floating gate electrode juxtaposed with and extending beyond the boundaries of the insulated gate, a pair of programming electrodes constituted by planar regions of the other conductivity type in the substrate, including a writing electrode and an erasing electrode each having an insulated gate of a thickness permitting junction crossing by hot carriers in partial overlap with floating gate electrode for capacitative coupling thereto, the region of overlap at said writing electrode being larger than that at said erasing electrode, and a diffusion region of the one conductivity type in said substrate next to and at a small distance from said writing electrode and having a surface area smaller than that of said writing electrode,

Abstract: A storage transistor includes a semiconductor substrate having formed therein a source region and a drain region spaced from said source region forming a channel region therebetween. A gate electrode is disposed over said channel region and a layer of storage medium has a first portion extending between the channel region and the gate electrode and a second portion extending laterally outside from between the channel region and the gate electrode, the ratio of the area of the second portion to the area of the first portion being in the range of 2 to 3. A first partial gate insulator layer is disposed between the channel region and the layer of storage medium and has a thickness ranging between 100 and 200 A.U., while a second partial gate insulator layer is disposed between the layer of storage medium and the gate electrode and has a thickness in the range of between 200 and 500 A.U.

Abstract: A programmable non-volatile semiconductor memory cell consisting of an n-channel insulated gate field effect transistor comprising a gate electrode which is floating with respect to potential, and enclosed on all sides by an insulating material and which, in its surface expansion, extends with electrode parts beyond a channel region of the insulated gate field effect transistor, which channel region is arranged on a surface of a monocrystalline semiconductor substrate, and which gate electrode is coupled capacitively by means of two electrode parts of different size via an insulated gate, to respective programming electrodes wherein an erase electrode to which an erase signal is capable of being applied, is created by a first planar zone forming a pn-junction with the semiconductor substrate and which, together with a first electrode part of the gate electrode, forms a first capacitance which is substantially smaller than a second capacitance between a second electrode part and a write electrode to which a wr

Abstract: The circuit of the current source comprises two enhancement IGFET pairs connected in series and one enhancement current source IGFET. All of the IGFETs show the same conductivity (p-channel or n-channel) and the two IGFET pairs are connected between the supply voltage and the substrate. The common connection point of the first IGFET pair is connected to the gate electrode of the substrate IGFET of the second IGFET pair and the common connection point of the second IGFET pair is fed to the gate of the current source IGFET.

Abstract: An insulated gate field-effect transistor is formed with an intermediate floating gate disposed between the gate electrode and the channel region, said floating gate including a control part extending laterally from between the gate electrode and channel region. Said intermediate floating gate including said control part are embedded in partial layers of dielectric material, said dielectric material electrically isolating said control part from at least one auxiliary electrode to which a voltage may be fed with respect to the substrate for capacitive coupling to the control part whereby the threshold voltage of the insulated gate field-effect transistor may be adjusted within a limited range.

Abstract: A programmable nonvolatile FET storage cell comprising crosswise to the ribbonlike source region as well as to the drain region a ribbonlike reading electrode and a separate ribbonlike writing electrode. Both electrodes are disposed upon a gate insulator layer into which a storage medium is embedded which is common to both electrodes.

Abstract: This relates to a monolithic dual-dielectric cell (DDC) memory array with a DDCFET matrix. The substrate zones of these DDCFETs are inserted into a substrate body having islands for decoder logic and potential selection integrated MISFET circuits. These circuits provide potentials to bitwise write, erase or read the matrix.