Patents by Inventor Fritz H. Gaensslen

Fritz H. Gaensslen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4274105
    Abstract: The sensitivity of the threshold voltage in MOSFET devices to changes in substrate voltage may be reduced at a given temperature by the introduction of sufficiently deep energy level, low diffusivity impurities into the depletion region under the gate of the MOSFET.
    Type: Grant
    Filed: December 29, 1978
    Date of Patent: June 16, 1981
    Assignee: International Business Machines Corporation
    Inventors: Billy L. Crowder, Fritz H. Gaensslen, Richard C. Jaeger
  • Patent number: 4268952
    Abstract: A method is disclosed for fabricating structures having electrically conductive regions such as high resolution semiconductor device and circuit designs which require only low resolution alignment steps during fabrication. The method is used to fabricate metal semiconductor field effect transistors (MESFET) and metal oxide semiconductor field effect transistors (MOSFET) devices and incorporates the following features. A device with very small (i.e. submicron) dimensions is positioned in a relatively large device well such that the exact position of the device in its well is not critical. Isolation and interconnection of devices in different wells is achieved by standard masking and alignment techniques with a resolution corresponding to the larger dimensions of the device wells.
    Type: Grant
    Filed: April 9, 1979
    Date of Patent: May 26, 1981
    Assignee: International Business Machines Corporation
    Inventors: Fritz H. Gaensslen, Eberhard A. Spiller
  • Patent number: 4128670
    Abstract: A method and structure for polysilicon lines which include a silicide layer for providing a low sheet resistance. The invention may be employed in a polysilicon gate MOSFET process for integrated circuits as well as other integrated structures. In the method a first layer of polysilicon is deposited followed by a deposition of a metal of the silicide forming type. Another polysilicon layer is then deposited on top of the silicide forming metal to produce a three layer structure. The three layer structure is subjected to heat, for example, during the reoxidation step in a gate fabrication process, the metal reacts with the polysilicon at two reaction fronts to form a silicide. The resultant silicide has a much lower resistivity than doped polysilicon and therefore provides a second conductive layer which can be used more compatibly and efficiently in connection with the normal metal layer employed in integrated circuits to give a two-dimensional degree of freedom for the distribution of signals.
    Type: Grant
    Filed: November 11, 1977
    Date of Patent: December 5, 1978
    Assignee: International Business Machines Corporation
    Inventor: Fritz H. Gaensslen