Abstract: A method and system for automatically producing clock signals for sampling data signals at different data rates via a phase locked loop, wherein in a synchronization process by means of the phase locked loop, a data signal is sampled successively using a clock signal at different frequencies, which are associated with different transmission protocols, and is checked for the presence of protocol identification information associated with the selected clock signal, until protocol identification information is detected such that the frequency resolution of the phase locked loop is advantageously increased, and the synchronization of the clock signal to the data signal is improved.

Abstract: The device converts a clock signal into a second clock signal having a different clock rate. This allows converting a first data signal into a second data signal having an altered data rate. Controlling the frequency dividers particularly in the feedback path of the phase-locked loops enables matching to the different data rates and conversion between both data signals DS1 into DS2, or DS2 into DS1.