Abstract: This is a fabrication process for complementary III-V HFETs in which devices are built side-by-side in doped-areas, known as "tubs", grown by molecular beam epitaxy on indium phosphide (InP) substrates, or other material systems such as materials grown on GaAs substrates. The layers grown are a semi-insulating buffer layer of InAlAs, a InGaAs channel, an InAlAs barrier layer and finally an InGaAs cap layer. All layers are lattice matched or pseudomorphic to the InP substrate. After mesa etching of areas around the transistor, a high temperature silicon nitride (Si.sub.3 N.sub.4) layer is deposited using chemical vapor deposition, and photoresist is deposited. Then n-well and p-well areas are formed in turn, with appropriate ion-implantation, stripping of the photoresist, and annealing to activate the dopants. Then the Si.sub.3 N.sub.4 is stripped and the samples thoroughly cleaned. Then, the refractory gate metal is sputtered, delineated with photoresist and reactive ion etch procedures.