Abstract: A phase regulating circuit which converts a slot clock signal at an input into a slot-free clock signal with a low jitter at an output, comprises a phase discriminator, two identical frequency dividers and a regulating and oscillator circuit. The regulating and oscillator circuit comprises a quartz crystal oscillator which supplies an auxiliary frequency, and an adding counter which generates a further signal with a further frequency. One control input of the adding counter is connected for this purpose to the output of the phase discriminator, while a second input of the adding counter is connected to the output of the quartz crystal oscillator. The auxiliary frequency and the further frequency are each connected to an input of an EXCLUSIVE OR gate by which they are added by regular polarity reversal. From this added frequency, a frequency divider obtains the frequency of the clock signal.

Abstract: A digital frequency divider, for producing an output signal related in frequency to an input signal by the ratio less than unity Z/N, incorporates an exclusive-OR gate and three frequency dividers having divisors m, n and k. The fraction Z/N is realized where n and k are integers, and the divisor m is chosen by: ##EQU1## When m is not an integral number, its corresponding divider is embodied by a cascaded divider circuit made up of two or more cascaded units each including an exclusive-OR gate and at least two frequency dividers connected to yield a fractional divisor.