Patents by Inventor Frode Heggelund

Frode Heggelund has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11030783
    Abstract: A graphics processor that performs early depth tests for primitives in respect of patches of a render output, and depth tests for sampling positions of the render output, maintains a per patch depth buffer that stores depth values for patches for use by the patch early depth test and a per sample depth buffer. When processing of a render output is stopped before the render output is finished, the per sample depth values in the per sample depth buffer are written to storage so that those values can be restored, but the per patch depth value information in the per patch depth buffer is discarded. Then, when processing of the render output is resumed, the per sample depth buffer values are loaded into a per sample depth buffer, and the loaded per sample depth buffer values are also used to restore the per patch depth buffer.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: June 8, 2021
    Assignee: Arm Limited
    Inventors: Andreas Due Engh-Halstvedt, Alexander Eugene Chalfin, Frode Heggelund
  • Patent number: 10957082
    Abstract: When performing conservative rasterisation in a graphics processing pipeline, modified edge information that accounts for an error in the dimensions of a primitive is determined by a primitive set-up stage. That modified edge information is then used by a rasterisation stage to determine whether the primitive covers one or more sampling points associated with pixels to be displayed. The same modified edge information can also be used to determine if the pixels are fully covered by the primitive irrespective of any rounding effects (errors) in the position of the (vertices of the) primitive.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: March 23, 2021
    Assignee: Arm Limited
    Inventor: Frode Heggelund
  • Patent number: 10937233
    Abstract: Disclosed herein is a bounding box that can be generated for a set of one or more primitive(s) and then passed to a rasteriser circuit for use thereby when generating the graphics fragments to be processed. The bounding box generation integrates a scissor test and allows primitives for which an initial bounding box has zero intersection with a specified scissor box to be discarded, whereas for primitives whose initial bounding box does intersect the scissor box, a new bounding box can be generated for output based on the area of intersection.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: March 2, 2021
    Assignee: Arm Limited
    Inventors: Ole Magnus Ruud, Frode Heggelund
  • Publication number: 20210027533
    Abstract: Disclosed herein is a bounding box that can be generated for a set of one or more primitive(s) and then passed to a rasteriser circuit for use thereby when generating the graphics fragments to be processed. The bounding box generation integrates a scissor test and allows primitives for which an initial bounding box has zero intersection with a specified scissor box to be discarded, whereas for primitives whose initial bounding box does intersect the scissor box, a new bounding box can be generated for output based on the area of intersection.
    Type: Application
    Filed: July 22, 2019
    Publication date: January 28, 2021
    Applicant: Arm Limited
    Inventors: Ole Magnus Ruud, Frode Heggelund
  • Patent number: 10769838
    Abstract: A graphics processing system can divide a render output into plural larger patches, with each larger patch encompassing plural smaller patches. A rasteriser of the system tests a larger patch against a primitive to be processed to determine if the primitive covers the larger patch. When it is determined that the primitive only partially covers the larger patch, the larger patch is sub-divided into plural smaller patches and at least one of the smaller patches is re-tested against the primitive. Conversely, when it is determined that the primitive completely covers the larger patch, the larger patch is output from the rasteriser in respect of the primitive for processing by a subsequent stage, of the graphics processing system. The system can provide efficient, hierarchal, processing of primitives, whilst helping to prevent the output of the rasteriser from becoming blocked.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: September 8, 2020
    Assignee: Arm Limited
    Inventors: Frode Heggelund, Toni Viki Brkic, Christian Vik Grovdal, Lars Oskar Flordal
  • Patent number: 10733782
    Abstract: To perform a graphics processing operation for the entirety of an area of a render output being generated by a graphics processor, a command to draw a primitive occupying the entire area of the render output is issued to the graphics processor. The graphics processor draws the primitive by determining the vertices to use for the primitive from the area of the render output. In a tile-based graphics processor at least, the graphics processor in an embodiment also determines whether it is unnecessary to process the graphics processing command for a rendering tile and when it is determined that processing the graphics processing command for the rendering tile is unnecessary, the graphics processor omits processing the graphics processing command for the rendering tile.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: August 4, 2020
    Assignee: Arm Limited
    Inventors: Frode Heggelund, Andreas Due Engh-Halstvedt, Christian Vik Grovdal
  • Patent number: 10726610
    Abstract: A graphics processing system maintains a fragment tracking record that stores metadata relating to one or more previously received primitives. The metadata can indicate that the one or more previously received primitives are suitably covered by a subsequently received primitive such that one or more fragment processing operations need not be performed in respect of those one or more previously received primitives. The metadata stored for the one or more previously received primitives can then later be queried by one or more later stages of the graphics processing system to determine whether one or more fragments for the one or more previously received primitives can be at least partially discarded or “killed”.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: July 28, 2020
    Assignee: Arm Limited
    Inventors: Frode Heggelund, Toni Viki Brkic, Christian Vik Grovdal, Lars Oskar Flordal
  • Publication number: 20200111247
    Abstract: To perform a graphics processing operation for the entirety of an area of a render output being generated by a graphics processor, a command to draw a primitive occupying the entire area of the render output is issued to the graphics processor. The graphics processor draws the primitive by determining the vertices to use for the primitive from the area of the render output. In a tile-based graphics processor at least, the graphics processor in an embodiment also determines whether it is unnecessary to process the graphics processing command for a rendering tile and when it is determined that processing the graphics processing command for the rendering tile is unnecessary, the graphics processor omits processing the graphics processing command for the rendering tile.
    Type: Application
    Filed: October 5, 2018
    Publication date: April 9, 2020
    Applicant: Arm Limited
    Inventors: Frode Heggelund, Andreas Due Engh-Halstvedt, Christian Vik Grovdal
  • Publication number: 20200074721
    Abstract: A graphics processing system maintains a fragment tracking record that stores metadata relating to one or more previously received primitives. The metadata can indicate that the one or more previously received primitives are suitably covered by a subsequently received primitive such that one or more fragment processing operations need not be performed in respect of those one or more previously received primitives. The metadata stored for the one or more previously received primitives can then later be queried by one or more later stages of the graphics processing system to determine whether one or more fragments for the one or more previously received primitives can be at least partially discarded or “killed”.
    Type: Application
    Filed: August 29, 2018
    Publication date: March 5, 2020
    Applicant: Arm Limited
    Inventors: Frode Heggelund, Toni Viki Brkic, Christian Vik Grovdal, Lars Oskar Flordal
  • Patent number: 10580113
    Abstract: A tile-based graphics processing system comprises a graphics processing pipeline comprising a plurality of processing stages, including at least a rasteriser that rasterises input primitives to generate graphics fragments to be processed, and a renderer that processes fragments generated by the rasteriser to generate rendered fragment data, and a tile buffer configured to store data locally to the graphics processing pipeline. The graphics processing system is operable to cause data for use when performing graphics processing operations for each tile of a set of plural tiles of a plurality of tiles to be loaded into the tile buffer before causing graphics processing operations to be performed for any of the tiles of the set of plural tiles.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: March 3, 2020
    Assignee: Arm Limited
    Inventors: Lars Oskar Flordal, Toni Viki Brkic, Christian Vik Grovdal, Andreas Due Engh-Halstvedt, Frode Heggelund
  • Publication number: 20190188896
    Abstract: A graphics processing system can divide a render output into plural larger patches, with each larger patch encompassing plural smaller patches. A rasteriser of the system tests a larger patch against a primitive to be processed to determine if the primitive covers the larger patch. When it is determined that the primitive only partially covers the larger patch, the larger patch is sub-divided into plural smaller patches and at least one of the smaller patches is re-tested against the primitive. Conversely, when it is determined that the primitive completely covers the larger patch, the larger patch is output from the rasteriser in respect of the primitive for processing by a subsequent stage, of the graphics processing system. The system can provide efficient, hierarchal, processing of primitives, whilst helping to prevent the output of the rasteriser from becoming blocked.
    Type: Application
    Filed: December 13, 2018
    Publication date: June 20, 2019
    Applicant: Arm Limited
    Inventors: Frode Heggelund, Toni Viki Brkic, Christian Vik Grovdal, Lars Oskar Flordal
  • Patent number: 10311016
    Abstract: A graphics processing pipeline includes a rasteriser, an early culling tester, a renderer, a late culling tester, and a culling test data buffer that stores data values for use by the early and late culling testers. The testing of fragments by the early and late culling testers is controlled in accordance with a first set of state information indicative of when a culling test operation to be used to determine whether to cull the fragments is to be performed, and a second set of state information indicative of when to determine whether to update the culling test data buffer with data for the fragments based on a culling test operation, allocated to the fragments.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: June 4, 2019
    Assignee: Arm Limited
    Inventors: Frode Heggelund, Toni Viki Brkic, Reimar Gisbert Döffinger
  • Publication number: 20190108610
    Abstract: A tile-based graphics processing system comprises a graphics processing pipeline comprising a plurality of processing stages, including at least a rasteriser that rasterises input primitives to generate graphics fragments to be processed, and a renderer that processes fragments generated by the rasteriser to generate rendered fragment data, and a tile buffer configured to store data locally to the graphics processing pipeline. The graphics processing system is operable to cause data for use when performing graphics processing operations for each tile of a set of plural tiles of a plurality of tiles to be loaded into the tile buffer before causing graphics processing operations to be performed for any of the tiles of the set of plural tiles.
    Type: Application
    Filed: October 5, 2018
    Publication date: April 11, 2019
    Applicant: Arm Limited
    Inventors: Lars Oskar Flordal, Toni Viki Brkic, Christian Vik Grovdal, Andreas Due Engh-Halstvedt, Frode Heggelund
  • Patent number: 10204391
    Abstract: A tile-based graphics processing pipeline that uses primitive lists that can encompass plural rendering tiles includes a primitive list reading unit that reads primitive lists for a tile being rendered to determine primitives to be processed for the tile and a rasterizer that rasterizes input primitives to generate graphics fragments to be processed. The pipeline further comprises a comparison unit between the primitive list reading unit and the rasterizer that for primitives that have been read from primitive lists that include plural rendering tiles, compares the location of the primitive in the render target to the location of the tile being rendered, and then either sends the primitive onwards to the rasterizer if the comparison determines that the primitive could lie at least partially within the tile, or does not send the primitive to the rasterizer if the comparison determines that the primitive definitely does not lie within the tile.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: February 12, 2019
    Assignee: Arm Limited
    Inventors: Frode Heggelund, Jorn Nystad
  • Patent number: 10204440
    Abstract: A graphics processing system generates interpolated vertex shaded attribute data for plural sampling points of plural fragments of a quad fragment that is being used to sample a primitive. The interpolated vertex shaded attribute data for the plural sampling points is generated using a reference position for the quad fragment that is defined with respect to a first coordinate system, together with rotated sampling point delta values for the primitive that are defined with respect to a second coordinate system. The rotated sampling point delta values allow the interpolated vertex shaded attribute data to be generated more efficiently for the plural sampling points.
    Type: Grant
    Filed: July 23, 2016
    Date of Patent: February 12, 2019
    Assignee: Arm Limited
    Inventors: Frode Heggelund, Jorn Nystad
  • Publication number: 20180349315
    Abstract: A graphics processing pipeline includes a rasteriser, an early culling tester, a renderer, a late culling tester, and a culling test data buffer that stores data values for use by the early and late culling testers. The testing of fragments by the early and late culling testers is controlled in accordance with a first set of state information indicative of when a culling test operation to be used to determine whether to cull the fragments is to be performed, and a second set of state information indicative of when to determine whether to update the culling test data buffer with data for the fragments based on a culling test operation, allocated to the fragments.
    Type: Application
    Filed: May 30, 2017
    Publication date: December 6, 2018
    Applicant: ARM Limited
    Inventors: Frode Heggelund, Toni Viki Brkic, Reimar Gisbert Döffinger
  • Publication number: 20180300915
    Abstract: When performing conservative rasterisation in a graphics processing pipeline, modified edge information that accounts for an error in the dimensions of a primitive is determined by a primitive set-up stage. That modified edge information is then used by a rasterisation stage to determine whether the primitive covers one or more sampling points associated with pixels to be displayed. The same modified edge information can also be used to determine if the pixels are fully covered by the primitive irrespective of any rounding effects (errors) in the position of the (vertices of the) primitive.
    Type: Application
    Filed: March 23, 2018
    Publication date: October 18, 2018
    Applicant: Arm Limited
    Inventor: Frode Heggelund
  • Patent number: 9805447
    Abstract: When carrying out a second, higher level of anti-aliasing such as 8×MSAA, in a graphics processing pipeline 1 configured to “natively” support a first level of anti-aliasing, such as 4×MSAA, the rasterization stage 3, early Z (depth) and stencil test stage 4, late Z (depth) and stencil test stage 7, blending stage 9, and downsampling and writeback (multisample resolve) stage 11 of the graphics processing pipeline 1 process each graphics fragment or pixel that they receive for processing in plural processing passes, each such processing pass processing a sub-set of the sampling points that the fragment represents, but the fragment shader 6 is configured to process each graphics fragment in a processing pass that processes all the sampling points that the fragment represents in parallel, so as to ensure compliance with the desired higher level of multisampled anti-aliasing.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: October 31, 2017
    Assignee: Arm Limited
    Inventors: Andreas Engh-halstvedt, Jorn Nystad, Frode Heggelund, Ronny Pedersen
  • Patent number: 9619929
    Abstract: A graphics processing apparatus and method of graphics processing is disclosed. Obscuration identification circuitry is configured to receive graphics fragments from rasterization circuitry and to identify an obscuration condition if a received graphics fragment, in combination with at least one previously received graphics fragment, will obscure at least one further previously received graphics fragment. Process killing circuitry is configured to prevent further processing occurring in the graphics processing apparatus with respect to the at least one further previously received graphics fragment if the obscuration identification circuitry identifies the obscuration condition.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: April 11, 2017
    Assignee: ARM Limited
    Inventors: Ian Victor Devereux, Simon Jones, Frode Heggelund, Toni Viki Brkic
  • Patent number: 9607390
    Abstract: A technique is provided for performing rasterisation of input primitives to generate graphics fragments to be processed to generate output data. The technique comprises determining a bounding box for an input primitive, and performing a multi-level patch analysis, each patch having an array of grid points defining boundaries of a set of sub-patches within that patch. The technique further comprises, when performing patch analysis of a selected patch, performing a bounding box evaluation step to determine if a condition exists where the bounding box does not cover any of the grid points, or if a special grid point coverage condition exists, and in the presence of the condition, adopting an alternative operation for that selected patch instead of a default operation. The alternative operation is configured to determine whether the primitive at least partially covers any of the sub-patches of the selected patch.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: March 28, 2017
    Assignee: ARM Limited
    Inventors: Frode Heggelund, Mukesh Haresh Lahori