Abstract: An electronic device comprising a system on chip and an external module. The system on chip includes a plurality of internal subsystems and a power management system including a plurality of internal voltage regulators which supply power to the plurality of internal subsystems. Each of the internal voltage regulators has an associated current limiter. The external module includes at least one external voltage regulator which can provide power to at least one of the internal subsystems. The power management system during a start-up phase enables the internal voltage regulators and the current limiters and in a subsequent phase determines an externally powered set of the internal subsystems, disables the corresponding internal voltage regulators, and disables the current limiters associated with the internal subsystems not externally powered.

Abstract: A circuit portion comprises a DCDC converter that provides current to one of a plurality of loads at a time. A controller detects when a voltage across an under-supplied load of the plurality of loads is below a first threshold. Channel logic circuitry provides current from the converter to the under-supplied load in response to the controller detecting that the voltage is below the first threshold. A voltage regulator provides current to the under-supplied load when the voltage is below a second threshold.

Abstract: A method is disclosed for producing an output clock signal with a target frequency using an oscillator circuit portion configured to receive a control value and produce an output clock signal with a frequency dependent on the control value. In one embodiment, the method comprises providing a first control value to the oscillator circuit portion corresponding to the target frequency, so as to cause the oscillator circuit portion to produce the output clock signal with a first frequency, comparing the output clock signal with a reference clock signal having a reference frequency to determine an offset between the first frequency and the target frequency, and providing a second control value to the oscillator circuit portion that differs from the first control value by a magnitude calculated with reference to the determined offset, to cause the oscillator circuit portion to produce the output clock signal with a second frequency.

Abstract: A processing apparatus has a processor comprising a plurality of deferred-push processor registers and processor-register control circuitry. The processor-register control circuitry comprises a plurality of status registers, each status register corresponding to a different respective deferred-push register. The processor-register control circuitry is configured to: detect a write of a new value to a register of the deferred-push registers; and determine whether the status register for the deferred-push register has a first value, indicative of an unsaved status for the deferred-push register. The processor-control circuitry is configured, when the status register has the first value, to: read a current value from the deferred-push register before the writing of the new value to the deferred-push register completes; write the current value to a memory; and set the status register for the deferred-push register to a second value, indicative of a saved status for the deferred-push register.

Abstract: A clock selector circuit receives a first input clock signal (CLK1) having a first frequency, and a second input clock signal (CLK2) having a second frequency. A phase difference detector is configured to detect when a phase difference occurs, over time, between the first input clock signal (CLK1) and the second input clock signal (CLK2), determined using when a clock edge crosses zero, and to signal this zero crossing to switching circuitry. The switching circuitry is configured, in response to receiving a zero-crossing signal from the phase difference detector, to detect an edge of opposite type to the predetermined type in the first input clock signal (CLK1) or in the second input clock signal (CLK2), and, in response to detecting said edge of opposite type, to switch an output clock signal (CLK_OUT) between the first input clock signal (CLK1) and the second input clock signal (CLK2).

Abstract: A method of operating a display system consisting of a plurality of light emitting diodes (LEDs) is disclosed. The LEDs are arranged in a plurality of groups and an integrated circuit provides power to the LEDs through a plurality of output pins connected to respective groups. The integrated circuit selectively determines the states of the output pins to illuminate the groups of LEDs in a repeating sequence such that each group is illuminated for a time dependent on a number of groups and a compensation factor. The compensation factor is dependent on at least a number of LEDs in the group.

Abstract: An electronic device comprising a system on chip and an external module. The system on chip includes a plurality of internal subsystems and a power management system including a plurality of internal voltage regulators which supply power to the plurality of internal subsystems. Each of the internal voltage regulators has an associated current limiter. The external module includes at least one external voltage regulator which can provide power to at least one of the internal subsystems. The power management system during a start-up phase enables the internal voltage regulators and the current limiters and in a subsequent phase determines an externally powered set of the internal subsystems, disables the corresponding internal voltage regulators, and disables the current limiters associated with the internal subsystems not externally powered.

Abstract: A clock selector circuit receives a first input clock signal (CLK1) having a first frequency, and a second input clock signal (CLK2) having a second frequency. A phase difference detector is configured to detect when a phase difference occurs, over time, between the first input clock signal (CLK1) and the second input clock signal (CLK2), determined using when a clock edge crosses zero, and to signal this zero crossing to switching circuitry. The switching circuitry is configured, in response to receiving a zero-crossing signal from the phase difference detector, to detect an edge of opposite type to the predetermined type in the first input clock signal (CLK1) or in the second input clock signal (CLK2), and, in response to detecting said edge of opposite type, to switch an output clock signal (CLK_OUT) between the first input clock signal (CLK1) and the second input clock signal (CLK2).

Abstract: A method is disclosed for producing an output clock signal with a target frequency using an oscillator circuit portion configured to receive a control value and produce an output clock signal with a frequency dependent on the control value. In one embodiment, the method comprises providing a first control value to the oscillator circuit portion corresponding to the target frequency, so as to cause the oscillator circuit portion to produce the output clock signal with a first frequency, comparing the output clock signal with a reference clock signal having a reference frequency to determine an offset between the first frequency and the target frequency, and providing a second control value to the oscillator circuit portion that differs from the first control value by a magnitude calculated with reference to the determined offset, to cause the oscillator circuit portion to produce the output clock signal with a second frequency.

Abstract: A method is disclosed for producing an output clock signal with a target frequency using an oscillator circuit portion configured to receive a control value and produce an output clock signal with a frequency dependent on the control value. In one embodiment, the method comprises providing a first control value to the oscillator circuit portion corresponding to the target frequency, so as to cause the oscillator circuit portion to produce the output clock signal with a first frequency, comparing the output clock signal with a reference clock signal having a reference frequency to determine an offset between the first frequency and the target frequency, and providing a second control value to the oscillator circuit portion that differs from the first control value by a magnitude calculated with reference to the determined offset, to cause the oscillator circuit portion to produce the output clock signal with a second frequency.

Abstract: A method is disclosed for producing an output clock signal with a target frequency using an oscillator circuit portion configured to receive a control value and produce an output clock signal with a frequency dependent on the control value. In one embodiment, the method comprises providing a first control value to the oscillator circuit portion corresponding to the target frequency, so as to cause the oscillator circuit portion to produce the output clock signal with a first frequency, comparing the output clock signal with a reference clock signal having a reference frequency to determine an offset between the first frequency and the target frequency, and providing a second control value to the oscillator circuit portion that differs from the first control value by a magnitude calculated with reference to the determined offset, to cause the oscillator circuit portion to produce the output clock signal with a second frequency.

Abstract: This document relates to apparatus and methods to store and retrieve trace information in on-chip system memory of microcontrollers. A microcontroller comprises a microprocessor and a memory device accessible through a data bus and an address bus coupled to the microprocessor. The microcontroller includes on-chip debug logic coupled to the microprocessor. Trace data can be retrieved from system memory using a debug port of the debug logic. A system in accordance with the present invention will lower the cost of implementation of trace features in microcontrollers, and strongly reduce the cost of supporting such features in debug tools.

Abstract: Methods and systems are provided for debugging a program executing on a processor. In a first implementation, a processing system includes a processor configured for switching to a debug mode from a non-debug mode upon executing a software breakpoint. The system may include a program memory configured to hold instructions for a program, where the software breakpoint replaces at least one of the instructions. The system may also include an instruction replacement register separate from the program memory that is configured to receive the replaced instruction from any of the processor and an external debugger. The system may further include a control component that controls whether the processor fetches a next instruction for execution from the program memory or from the instruction replacement register.

Abstract: A system for debugging a device under test may include a processor register with a program count and a debug program register that receives the program count upon execution of an instruction by a processor. In one implementation, a microcontroller under test by a debugger is accessed using a serial interface, such as a JTAG interface. The interface can communicate directly with a debug register to retrieve program count values, both when the microcontroller is halted and when it is executing instructions. The polling interval to retrieve the program count values may be adjusted by a user of the debugger based on considerations such as bandwidth and accuracy. The microcontroller may transmit the program count value to the debug register from a processing register that is not accessible to the debugger.

Abstract: A system and method for executing a sequential data memory access through a serial access port is provided. The system may include a memory access controller to receive a block access command and successively access data elements in the block. In certain implementations, a test device, such as a JTAG host, transmits a block read or write command specifying a start address and an increment value to an embedded device under test, whereupon a memory access controller in the embedded device sequentially accesses the data at the start address, increments the address by the increment value, accesses the data at the incremented address, and repeats this procedure to sequentially access each of the remaining data elements in the block.

Abstract: A system and methods to transfer data between a testing interface and an IC. The system may include a synchronization subsystem to monitor the transitions of the test interface clock and/or IC clock to determine a clock adjustment appropriate to substantially synchronize the clocks. In certain implementations, a synchronization unit on an IC under test counts a predetermined number of transitions of an internal clock of an embedded device and generates a signal upon reaching a terminal count, which signal is received by a host controller associated with a JTAG test fixture. In such implementations, the host controller determines the number of IC clock cycles that occurred during the predetermined number of IC clock cycles and synthesizes a synchronized JTAG clock that is a integral fraction of the IC clock.

Abstract: Writing to a page of flash memory may include receiving write commands that are substantially independent of an internal architecture of the flash memory. In certain embodiments, two operand flash commands are received at a flash controller from a remote controller. In various implementations, the writing process may further include translating each two-operand write command into architecture-dependent flash commands; executing the architecture-dependent flash commands to fill a page buffer associated with the flash memory; and subsequently transferring contents of the page buffer to the page of flash memory.

Abstract: A system for configuring or testing memory may cycle a memory array while substantially concurrently performing other functional testing. In particular implementations, the system may configure, or cycle, a flash memory using a serial interface and test other functional units using the same serial interface substantially concurrently with cycling the flash memory. In some implementations, cycling the flash memory includes erasing and writing to the flash memory in specific patterns in order to dissipate charge that may have accumulated during a fabrication process.

Abstract: It is the object of the present invention to provide a mechanism to store and retrieve trace information in on-chip system memory of microcontrollers. A microcontroller comprises a microprocessor and a memory device accessible through a data bus and an address bus coupled to the microprocessor. The microcontroller includes on-chip debug logic coupled to the microprocessor. The on-chip debug logic includes a low speed debug port and a mechanism for temporarily storing trace data on the memory, wherein the trace data can be retrieved via the low speed debug port by a debug tool. A method and system in accordance with the present invention will lower the cost of implementation of trace features in microcontrollers, and strongly reduce the cost of supporting such features in debug tools.

Abstract: A microcontroller is disclosed. The microcontroller includes a central processor unit (CPU) and a Flash program memory in communication with the CPU via an instruction bus. The microcontroller includes an on-chip debug (OCD) logic coupled to the CPU. The OCD logic containing logic that detects a zero opcode on an instruction bus between the CPU and the Flash program memory to provide a program breakpoint. This is an advantage over prior art in that any number of such breakpoints can be inserted into the Flash program memory, without requiring the memory to be erased. A system and method in accordance with the present invention provides a vastly improved support for program breakpoints in Flash program memory-based microcontrollers with a minimum increase in on-chip debug logic and complexity.