Abstract: This document describes systems and techniques directed at an external wide-angle lens for imagers in electronic devices. An imager is disclosed that includes an image sensor and a lens stack, the lens stack including an external wide-angle lens, an internal lens, and four or more intermediate lenses. The imager has a first ratio of a projection at a vertex of the external wide-angle lens divided by a maximum focused dimension of the focal area being less than or equal to 0.15, a second ratio of a total length of the lens stack divided by the maximum focused dimension being less than or equal to 7.0, or a third ratio of a total transmission length of the imager divided by an entrance pupil diameter of the external wide-angle lens being between 1.2 and 2.6.

Abstract: A method for forming a package structure is provided, which includes recessing a substrate to form a trench, disposing a first stacked die package structure over the substrate, forming an underfill layer over the first stacked die package structure and in the trench, and forming a package layer over the underfill layer and in the trench.

Abstract: An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.

Abstract: A network management method and a network entity are provided. In the method, a detection result is obtained. One of multiple network slices is switched to another according to the detection result. The detection result is a result of detecting an image. Each network slice provides a network resource. The image is accessed through the network resource. Accordingly, a network setting parameter could be dynamically adjusted to save energy.

Abstract: An integrated circuit includes a plurality of transistors and a vertical local interconnection. The transistors include a plurality of gate components, a plurality of front-side source/drain epitaxies and a plurality of back-side source/drain epitaxies, wherein the front-side source/drain epitaxies are closer to a front-side side of the integrated circuit than the back-side source/drain epitaxies. The vertical local interconnection connects a first connected-one of the front-side source/drain epitaxies with a second connected-one of the back-side source/drain epitaxies. A covered-one of the gate components is located between the first connected-one and the second connected-one, the covered-one comprises an front-side portion, a back-side portion and a covered portion connecting the front-side portion with the back-side portion, and the vertical local interconnection crosses the covered portion and exposes the front-side portion and the back-side portion.

Abstract: The present disclosure provides a light-emitting device comprising a substrate with a topmost surface; a first semiconductor stack arranged on the substrate, and comprising a first top surface separated from the topmost surface by a first distance; a first bonding layer arranged between the substrate and the first semiconductor stack; a second semiconductor stack arranged on the substrate, and comprising a second top surface separated from the topmost surface by a second distance which is different form the first distance; a second bonding layer arranged between the substrate and the second semiconductor stack; a third semiconductor stack arranged on the substrate, and comprising third top surface separated from the topmost surface by a third distance; and a third bonding layer arranged between the substrate and the third semiconductor stack; wherein the first semiconductor stack, the second semiconductor stack, and the third semiconductor stack are configured to emit different color lights.

Abstract: A composite solid base catalyst, a manufacturing method thereof and a manufacturing method of glycidol are provided. The composite solid base catalyst includes an aluminum carrier and a plurality of calcium particles. The plurality of calcium particles are supported by the aluminum carrier. Beta basic sites of the composite solid base catalyst are 0.58 mmol/g-3.89 mmol/g.

Abstract: This disclosure relates to a polishing composition that includes an abrasive, at least two pH adjusters, a barrier film removal rate enhancer, a low-k removal rate inhibitor, and an azole-containing corrosion inhibitor. This disclosure also features a method of using the polishing composition to polish a substrate containing copper and silicon oxide.

Abstract: Provided in the present disclosure are a Zika/dengue vaccine and its application thereof. The present disclosure introduces a mutation into the E-protein FL fusion region of the Zika virus or dengue virus. Antigens with said mutations are unable to bind to antibodies that causes ADE. After immunization with the vaccine of the present disclosure acquired from the said antigens, production of FL epitope-induced antibodies can be prevented, thereby reducing or eliminating the ADE effect.

Abstract: An electronic device includes a first substrate, a first protrusion, a second protrusion and a plurality of third protrusions. The first substrate includes an edge, a first region, and a second region. The first substrate includes a surface. The first protrusion is in the first region. A maximum distance from the surface to a top surface of the first protrusion is defined as a first distance. The second protrusion is in the second region. A maximum distance from the surface to a top surface of the second protrusion is defined as a second distance. The first protrusion is disposed between two of the third protrusions. A maximum distance from the surface to a top surface of the third protrusion is defined as a third distance. The first distance is different from the second distance, and the third distance is less than the first distance.

Abstract: A non-fullerene acceptor polymer includes a structure represented by formula (I). Formula (I) is defined as in the specification. The non-fullerene acceptor polymer has an electron donating unit and an electron attracting end group. The non-fullerene acceptor polymer uses phenyl or its derivatives as the linker to form the polymer.

Abstract: In an indoor environment on fire, automatic deployment of sensors disposed on, beneath or over the floor to look upward the ceiling to observe a body of smoke and flame risen near the ceiling allows important information regarding states and dynamics of the body of smoke and flame to be gathered at an early stage of fire (e.g. before arrival of firefighters). By distributing the sensors over the indoor environment, the states and dynamics of the body of smoke and flame are monitored holistically (i.e. as a whole) even at the early stage of fire. Such information is useful to predict development of the fire. In one implementation, a sensor is held in an infrastructure sensor holder mounted on the ceiling during normal time. Upon detecting occurrence of fire, the sensor drops from the holder to land on the floor and orients a sensing direction vertically upward to perform monitoring.

Abstract: Disclosed is a method of manufacturing a semiconductor device. The method includes forming a patterned hardmask over an underlying target layer on a substrate; and performing plasma fabrication operations in parallel on the patterned hardmask and underlying target layer in a plasma etching chamber using a plasma etch gas and a selective source gas. The plasma operations include forming a protective cap on the patterned hardmask; and removing portions of the underlying layer that are not covered by the patterned hardmask. In various embodiments, the selective source gas includes a chemical compound that includes a halogen gas that can be dissociated into a metal and a halogen, and the plasma operations include dissociating the metal and the halogen in the selective source gas and forming a protective cap on the patterned hardmask using the metal that has been dissociated.

Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.

Abstract: An embodiment is a structure including a first package including a first die, and a molding compound at least laterally encapsulating the first die, a second package bonded to the first package with a first set of conductive connectors, the second package comprising a second die, and an underfill between the first package and the second package and surrounding the first set of conductive connectors, the underfill having a first portion extending up along a sidewall of the second package, the first portion having a first sidewall, the first sidewall having a curved portion and a planar portion.

Abstract: A method includes forming a first polymer layer to cover a metal pad of a wafer, and patterning the first polymer layer to form a first opening. A first sidewall of the first polymer layer exposed to the first opening has a first tilt angle where the first sidewall is in contact with the metal pad. The method further includes forming a metal pillar in the first opening, sawing the wafer to generate a device die, encapsulating the device die in an encapsulating material, performing a planarization to reveal the metal pillar, forming a second polymer layer over the encapsulating material and the device die, and patterning the second polymer layer to form a second opening. The metal pillar is exposed through the second opening. A second sidewall of the second polymer layer exposed to the second opening has a second tilt angle greater than the first tilt angle.

Abstract: Provided is an electronic package, in which a heat dissipating body is formed on an electronic device and is combined with a heat sink so that the electronic device, the heat dissipating body and the heat sink form a receiving space, and a heat dissipating material is formed in the receiving space and in contact with the heat sink and the electronic device, where a fluid regulating space is formed between the heat dissipating material and the heat dissipating body and is used as a volume regulating space for the heat dissipating material during thermal expansion and contraction.

Abstract: The present disclosure provides a dual-lens movement control method, which includes steps as follows. The tracking target is detected through the wide-angle lens, and the final tracking range is calculated; the magnification and the position are determined according to the final tracking range; the separate mode or the alignment mode is determined according to the magnification and the position.

Abstract: A semiconductor device structure and method for manufacturing the same are provided. The semiconductor device structure includes a substrate, a dielectric structure, a pad, a conductive structure, and a buffer structure. The dielectric structure is disposed on the substrate. The pad is embedded in the dielectric structure. The conductive structure is disposed on the pad. The buffer structure is disposed on the pad and separates the conductive structure from the dielectric structure. A coefficient of thermal expansion (CTE) of the buffer structure ranges between a CTE of the dielectric structure and a CTE of the conductive structure.

Abstract: A semiconductor device structure and method for manufacturing the same are provided. The semiconductor device structure includes a substrate, a dielectric structure, a pad, a conductive structure, and a buffer structure. The dielectric structure is disposed on the substrate. The pad is embedded in the dielectric structure. The conductive structure is disposed on the pad. The buffer structure is disposed on the pad and separates the conductive structure from the dielectric structure. A coefficient of thermal expansion (CTE) of the buffer structure ranges between a CTE of the dielectric structure and a CTE of the conductive structure.