Patents by Inventor Fu An TIEN
Fu An TIEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240338510Abstract: Systems and methods are provided for generating test patterns. In various embodiments, systems and methods are provided in which machine learning is utilized to generate the test patterns in a manner so that the test patterns conform with design rule check (DRC) specified for a particular semiconductor manufacturing process or for particular types of devices. A test pattern generation system includes test pattern generation circuitry which receives a noise image. The test pattern generation generates a pattern image based on the noise image, and further generates a test pattern based on the pattern image. The test pattern is representative of geometric shapes of an electronic device design layout that is free of design rule check violations.Type: ApplicationFiled: June 17, 2024Publication date: October 10, 2024Inventors: Fu-An Tien, Hsu-Ting Huang, Ru-Gun Liu
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Patent number: 12039247Abstract: Systems and methods are provided for generating test patterns. In various embodiments, systems and methods are provided in which machine learning is utilized to generate the test patterns in a manner so that the test patterns conform with design rule check (DRC) specified for a particular semiconductor manufacturing process or for particular types of devices. A test pattern generation system includes test pattern generation circuitry which receives a noise image. The test pattern generation generates a pattern image based on the noise image, and further generates a test pattern based on the pattern image. The test pattern is representative of geometric shapes of an electronic device design layout that is free of design rule check violations.Type: GrantFiled: August 9, 2021Date of Patent: July 16, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fu-An Tien, Hsu-Ting Huang, Ru-Gun Liu
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Patent number: 11675958Abstract: In a method of optimizing a lithography model in a lithography simulation, a mask is formed in accordance with a given layout, a wafer is printed using the mask, a pattern formed on the printed wafer is measured, a wafer pattern is simulated using a wafer edge bias table and the given mask layout, a difference between the simulated wafer pattern and the measured pattern is obtained, and the wafer edge table is adjusted according to the difference.Type: GrantFiled: July 30, 2021Date of Patent: June 13, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Fu An Tien, Hsu-Ting Huang, Ru-Gun Liu, Shih-Hsiang Lo
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Patent number: 11662657Abstract: A method for manufacturing a photo mask for a semiconductor device includes receiving a plurality of hotspot regions of a mask layout corresponding to the semiconductor device. The method further includes classifying the plurality of hotspot regions into two or more hotspot groups such that same or similar hotspot regions are classified into same hotspot groups. The hotspot groups includes a first hotspot group that has at least two hotspot regions. The method also includes correcting a first hotspot region of the first hotspot group to generate an enhancement of the first hotspot region and correcting other hotspot regions of the first hotspot group using the enhancement of the first hotspot region to generate enhancements of other hotspot regions of the first hotspot group.Type: GrantFiled: June 13, 2022Date of Patent: May 30, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Fu An Tien, Hsu-Ting Huang, Ru-Gun Liu
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Publication number: 20220308439Abstract: A method for manufacturing a photo mask for a semiconductor device includes receiving a plurality of hotspot regions of a mask layout corresponding to the semiconductor device. The method further includes classifying the plurality of hotspot regions into two or more hotspot groups such that same or similar hotspot regions are classified into same hotspot groups. The hotspot groups includes a first hotspot group that has at least two hotspot regions. The method also includes correcting a first hotspot region of the first hotspot group to generate an enhancement of the first hotspot region and correcting other hotspot regions of the first hotspot group using the enhancement of the first hotspot region to generate enhancements of other hotspot regions of the first hotspot group.Type: ApplicationFiled: June 13, 2022Publication date: September 29, 2022Inventors: Fu An TIEN, Hsu-Ting HUANG, Ru-Gun LIU
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Patent number: 11360379Abstract: A method for manufacturing a photo mask for a semiconductor device includes receiving a plurality of hotspot regions of a mask layout corresponding to the semiconductor device. The method further includes classifying the plurality of hotspot regions into two or more hotspot groups such that same or similar hotspot regions are classified into same hotspot groups. The hotspot groups includes a first hotspot group that has at least two hotspot regions. The method also includes correcting a first hotspot region of the first hotspot group to generate an enhancement of the first hotspot region and correcting other hotspot regions of the first hotspot group using the enhancement of the first hotspot region to generate enhancements of other hotspot regions of the first hotspot group.Type: GrantFiled: December 14, 2020Date of Patent: June 14, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Fu An Tien, Hsu-Ting Huang, Ru-Gun Liu
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Patent number: 11204897Abstract: A computer-implemented method includes executing, using a computer, a process including a main thread that receives a layout file. The layout file includes a first plurality of tags and compressed information blocks. Each tag of the first plurality is associated with a compressed information block. The method further includes decompressing the compressed information blocks using sub-threads and thereby obtaining decompressed information blocks. The sub-threads are created by the main thread, and each sub-thread corresponds to a compressed information block. The decompressed information blocks are combined into decompressed layout information. The decompressed file is partitioned and each partition is provided to a node of a distributed computing system for performing layout correction.Type: GrantFiled: October 30, 2019Date of Patent: December 21, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Fu An Tien, Changsheng Ying, Hsu-Ting Huang, Ru-Gun Liu
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Publication number: 20210365625Abstract: Systems and methods are provided for generating test patterns. In various embodiments, systems and methods are provided in which machine learning is utilized to generate the test patterns in a manner so that the test patterns conform with design rule check (DRC) specified for a particular semiconductor manufacturing process or for particular types of devices. A test pattern generation system includes test pattern generation circuitry which receives a noise image. The test pattern generation generates a pattern image based on the noise image, and further generates a test pattern based on the pattern image. The test pattern is representative of geometric shapes of an electronic device design layout that is free of design rule check violations.Type: ApplicationFiled: August 9, 2021Publication date: November 25, 2021Inventors: Fu-An Tien, Hsu-Ting Huang, Ru-Gun Liu
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Publication number: 20210357571Abstract: In a method of optimizing a lithography model in a lithography simulation, a mask is formed in accordance with a given layout, a wafer is printed using the mask, a pattern formed on the printed wafer is measured, a wafer pattern is simulated using a wafer edge bias table and the given mask layout, a difference between the simulated wafer pattern and the measured pattern is obtained, and the wafer edge table is adjusted according to the difference.Type: ApplicationFiled: July 30, 2021Publication date: November 18, 2021Inventors: Fu An TIEN, Hsu-Ting HUANG, Ru-Gun LIU, Shih-Hsiang LO
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Patent number: 11093683Abstract: Systems and methods are provided for generating test patterns. In various embodiments, systems and methods are provided in which machine learning is utilized to generate the test patterns in a manner so that the test patterns conform with design rule check (DRC) specified for a particular semiconductor manufacturing process or for particular types of devices. A test pattern generation system includes test pattern generation circuitry which receives a noise image. The test pattern generation generates a pattern image based on the noise image, and further generates a test pattern based on the pattern image. The test pattern is representative of geometric shapes of an electronic device design layout that is free of design rule check violations.Type: GrantFiled: September 3, 2019Date of Patent: August 17, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fu-An Tien, Hsu-Ting Huang, Ru-Gun Liu
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Patent number: 11080458Abstract: In a method of optimizing a lithography model in a lithography simulation, a mask is formed in accordance with a given layout, a wafer is printed using the mask, a pattern formed on the printed wafer is measured, a wafer pattern is simulated using a wafer edge bias table and the given mask layout, a difference between the simulated wafer pattern and the measured pattern is obtained, and the wafer edge table is adjusted according to the difference.Type: GrantFiled: September 26, 2019Date of Patent: August 3, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Fu An Tien, Hsu-Ting Huang, Ru-Gun Liu, Shih-Hsiang Lo
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Publication number: 20210103211Abstract: A method for manufacturing a photo mask for a semiconductor device includes receiving a plurality of hotspot regions of a mask layout corresponding to the semiconductor device. The method further includes classifying the plurality of hotspot regions into two or more hotspot groups such that same or similar hotspot regions are classified into same hotspot groups. The hotspot groups includes a first hotspot group that has at least two hotspot regions. The method also includes correcting a first hotspot region of the first hotspot group to generate an enhancement of the first hotspot region and correcting other hotspot regions of the first hotspot group using the enhancement of the first hotspot region to generate enhancements of other hotspot regions of the first hotspot group.Type: ApplicationFiled: December 14, 2020Publication date: April 8, 2021Inventors: Fu An TIEN, Hsu-Ting HUANG, Ru-Gun LIU
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Patent number: 10866506Abstract: A method for manufacturing a photo mask for a semiconductor device includes receiving a plurality of hotspot regions of a mask layout corresponding to the semiconductor device. The method further includes classifying the plurality of hotspot regions into two or more hotspot groups such that same or similar hotspot regions are classified into same hotspot groups. The hotspot groups includes a first hotspot group that has at least two hotspot regions. The method also includes correcting a first hotspot region of the first hotspot group to generate an enhancement of the first hotspot region and correcting other hotspot regions of the first hotspot group using the enhancement of the first hotspot region to generate enhancements of other hotspot regions of the first hotspot group.Type: GrantFiled: September 20, 2019Date of Patent: December 15, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Fu An Tien, Hsu-Ting Huang, Ru-Gun Liu
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Publication number: 20200133924Abstract: A computer-implemented method includes executing, using a computer, a process including a main thread that receives a layout file. The layout file includes a first plurality of tags and compressed information blocks. Each tag of the first plurality is associated with a compressed information block. The method further includes decompressing the compressed information blocks using sub-threads and thereby obtaining decompressed information blocks. The sub-threads are created by the main thread, and each sub-thread corresponds to a compressed information block. The decompressed information blocks are combined into decompressed layout information. The decompressed file is partitioned and each partition is provided to a node of a distributed computing system for performing layout correction.Type: ApplicationFiled: October 30, 2019Publication date: April 30, 2020Inventors: Fu An TIEN, Changsheng YING, Hsu-Ting HUANG, Ru-Gun LIU
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Publication number: 20200133115Abstract: A method for manufacturing a photo mask for a semiconductor device includes receiving a plurality of hotspot regions of a mask layout corresponding to the semiconductor device. The method further includes classifying the plurality of hotspot regions into two or more hotspot groups such that same or similar hotspot regions are classified into same hotspot groups. The hotspot groups includes a first hotspot group that has at least two hotspot regions. The method also includes correcting a first hotspot region of the first hotspot group to generate an enhancement of the first hotspot region and correcting other hotspot regions of the first hotspot group using the enhancement of the first hotspot region to generate enhancements of other hotspot regions of the first hotspot group.Type: ApplicationFiled: September 20, 2019Publication date: April 30, 2020Inventors: Fu An TIEN, Hsu-Ting HUANG, Ru-Gun LIU
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Publication number: 20200134131Abstract: Systems and methods are provided for generating test patterns. In various embodiments, systems and methods are provided in which machine learning is utilized to generate the test patterns in a manner so that the test patterns conform with design rule check (DRC) specified for a particular semiconductor manufacturing process or for particular types of devices. A test pattern generation system includes test pattern generation circuitry which receives a noise image. The test pattern generation generates a pattern image based on the noise image, and further generates a test pattern based on the pattern image. The test pattern is representative of geometric shapes of an electronic device design layout that is free of design rule check violations.Type: ApplicationFiled: September 3, 2019Publication date: April 30, 2020Inventors: Fu-An Tien, Hsu-Ting Huang, Ru-Gun Liu
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Publication number: 20200103764Abstract: In a method of optimizing a lithography model in a lithography simulation, a mask is formed in accordance with a given layout, a wafer is printed using the mask, a pattern formed on the printed wafer is measured, a wafer pattern is simulated using a wafer edge bias table and the given mask layout, a difference between the simulated wafer pattern and the measured pattern is obtained, and the wafer edge table is adjusted according to the difference.Type: ApplicationFiled: September 26, 2019Publication date: April 2, 2020Inventors: Fu An TIEN, Hsu-Ting HUANG, Ru-Gun LIU, Shih-Hsiang LO