Abstract: An optical system is provided and includes a fixed assembly, a movable element and a driving module. The fixed assembly has a main axis. The movable element is movable relative to the fixed assembly and coupled to a first optical element. The driving module is configured to drive the movable element to move relative to the fixed assembly. The driving module includes a first driving assembly and a second driving assembly, and the first driving assembly and the second driving assembly are individually operable.

Abstract: Various 3D cells, array structures and processes are disclosed. In an embodiment, a memory cell structure is provided that includes a vertical bit line, an insulator surrounding a first portion of vertical bit line, a continuous semiconductor layer surrounding the insulator and a second portion of the vertical bit line, and an extended portion of conductor material surrounding the continuous semiconductor layer. The memory cell structure also includes a first dielectric layer surrounding extended portion of conductor material, a first conductor layer surrounding the first dielectric layer, a second conductor layer surrounding the first conductor layer, a second dielectric layer on a top surface of the first and second conductor layers, a third dielectric layer on a bottom surface of the first and second conductor layers, a first gate on a top surface of the second dielectric layer, and a second gate on a bottom surface of the third dielectric layer.

Abstract: Various 3D memory cells, array structures, and processes are disclosed. In an embodiment, a 3D memory cell structure includes a vertical conductor core, an insulator surrounding the vertical conductor core, a semiconductor layer surrounding the insulator, charge trapping layers surrounding the semiconductor layer, and a word line layer surrounding at least a portion of the charge trapping layers.

Abstract: Various 3D array structures and processes are disclosed. In an embodiment, a word line staircase structure is provided that includes a plurality of word line layers alternately deposited with a plurality of insulating layers to form a stack and a first word line stairstep that includes all the layers of the stack. The staircase structure also includes one or more additional word line stairsteps such that each successive additional word line stairstep is formed to include less layers of the stack than the preceding word line stairstep to form the word line staircase structure. The stairstep structure also includes multiple contact holes formed in each word line stairstep to contact multiple word line layers within that word line stairstep.

Abstract: A quantum bit array is disclosed. In an embodiment, the quantum bit array includes a control gate coupled to a qubit and at least one pass gate coupled between the qubit and an adjacent qubit to control operation of the qubit of the quantum bit array, a bit line, and a first transistor channel that connects the bit line to the control gate. The array further comprises at least one word line coupled to the first transistor channel. The at least one word line selectively controls charge flow through the first transistor channel. The array further comprises a capacitor coupled to selectively store charge in the first transistor channel.

Abstract: Methods and apparatus for memory operations disclosed. In an embodiment, a method is provided for programming multiple-level cells in a memory array. The memory array includes a plurality of planes and each plane includes a plurality of bit lines. The method includes storing multiple data bits in a first group of planes, one data bit per plane. The multiple data bits are stored in bit line capacitances of the first group of planes. The method also includes programming a selected multiple-level cell in a selected plane according to the multiple data bits that are stored in the bit line capacitances of the first group of planes. The selected plane is not one of the first group of planes.

Abstract: Various 3D memory cells, array architectures, and processes are disclosed. In an embodiment, a memory cell structure is provided that includes a vertical bit line, a first semiconductor layer surrounding a first portion of the vertical bit line, and a first gate surrounding the first semiconductor layer. The memory cell structure also includes a second semiconductor layer surrounding a second portion of the vertical bit line, and a gate dielectric layer surrounding a third portion of the vertical bit line. The gate dielectric layer separates the first semiconductor layer and the first gate from the second semiconductor layer.

Abstract: Methods and apparatus for NAND flash memory are disclosed. In an embodiment, a NAND flash memory is provided that includes a plurality of bit lines connected to a plurality of bit line select gates, respectively, and a page buffer connected to the plurality of bit line select gates. The NAND flash memory also includes a plurality of load devices connected to the plurality of bit lines, respectively. The plurality of load devices are configured to provide load current during read operations.

Abstract: Various 3D cells, array structures and processes are disclosed. In an embodiment, a memory cell structure is provided that includes a vertical bit line, an insulator surrounding a first portion of vertical bit line, a continuous semiconductor layer surrounding the insulator and a second portion of the vertical bit line, and an extended portion of conductor material surrounding the continuous semiconductor layer. The memory cell structure also includes a first dielectric layer surrounding extended portion of conductor material, a first conductor layer surrounding the first dielectric layer, a second conductor layer surrounding the first conductor layer, a second dielectric layer on a top surface of the first and second conductor layers, a third dielectric layer on a bottom surface of the first and second conductor layers, a first gate on a top surface of the second dielectric layer, and a second gate on a bottom surface of the third dielectric layer.

Abstract: Various 3D memory cells, array structures, and processes are disclosed. In an embodiment, a 3D memory cell structure includes a vertical conductor core, an insulator surrounding the vertical conductor core, a semiconductor layer surrounding the insulator, charge trapping layers surrounding the semiconductor layer, and a word line layer surrounding at least a portion of the charge trapping layers.

Abstract: Various 3D array structures and processes are disclosed. In an embodiment, a word line staircase structure is provided that includes a plurality of word line layers alternately deposited with a plurality of insulating layers to form a stack and a first word line stairstep that includes all the layers of the stack. The staircase structure also includes one or more additional word line stairsteps such that each successive additional word line stairstep is formed to include less layers of the stack than the preceding word line stairstep to form the word line staircase structure. The stairstep structure also includes multiple contact holes formed in each word line stairstep to contact multiple word line layers within that word line stairstep.

Abstract: A quantum bit array is disclosed. In an embodiment, the quantum bit array includes a control gate coupled to a qubit and at least one pass gate coupled between the qubit and an adjacent qubit to control operation of the qubit of the quantum bit array, a bit line, and a first transistor channel that connects the bit line to the control gate. The array further comprises at least one word line coupled to the first transistor channel. The at least one word line selectively controls charge flow through the first transistor channel. The array further comprises a capacitor coupled to selectively store charge in the first transistor channel.

Abstract: Various 3D memory cells, array architectures, and processes are disclosed. In an embodiment, a memory cell structure is provided that is formed by a process of alternately depositing multiple semiconductor layers and sacrificial layers to form a stack, forming vertical bit line holes through the stack using a deep trench process, forming floating bodies in the semiconductor layers using an isotropic doping process through the bit line holes, depositing conductor material to fill the bit line holes, removing the sacrificial layers, depositing a gate dielectric layer between the semiconductor layers, and depositing gate material onto the gate dielectric layer.

Abstract: Various 3D memory cells, array architectures, and processes are disclosed. In an embodiment, a three-dimensional (3D) stackable memory cell structure is provided that includes a first material, a floating body semiconductor material that surrounds a first portion of the first material, a second material that surrounds a portion of the floating body semiconductor material, and a front gate material. The 3D stackable memory cell structure also includes a first dielectric layer located between the front gate material and the floating body semiconductor material, a back gate material, a second dielectric layer located between the back gate material and the floating body semiconductor material, and a second semiconductor material that surrounds a second portion of the first material and is directly connected to the floating body semiconductor material.

Abstract: Various 3D memory cells, array architectures, and processes are disclosed. In an embodiment, a memory cell structure is provided that is formed by a process of alternately depositing multiple semiconductor layers and sacrificial layers to form a stack, forming vertical bit line holes through the stack using a deep trench process, forming floating bodies in the semiconductor layers using an isotropic doping process through the bit line holes, depositing conductor material to fill the bit line holes, removing the sacrificial layers, depositing a gate dielectric layer between the semiconductor layers, and depositing gate material onto the gate dielectric layer.

Abstract: Various 3D memory cells, array architectures, and processes are disclosed. In an embodiment, a memory cell structure is provided that is formed by a process of alternately depositing multiple semiconductor layers and insulating layers to form a stack, forming vertical bit line holes through the stack using a deep trench process, and forming floating bodies in the semiconductor layers using an isotropic doping process through the bit line holes.

Abstract: A quantum bit array is disclosed. In an embodiment, the quantum bit array includes a control gate coupled to a qubit and at least one pass gate coupled between the qubit and an adjacent qubit to control operation of the qubit of the quantum bit array, a bit line, and a first transistor channel that connects the bit line to the control gate. The array further comprises at least one word line coupled to the first transistor channel. The at least one word line selectively controls charge flow through the first transistor channel. The array further comprises a capacitor coupled to selectively store charge in the first transistor channel.

Abstract: Advanced structures having MOSFET transistors and metal layers are disclosed. In one embodiment, a transistor structure is provided that includes a first transistor layer, a second transistor layer located under the first transistor layer, a first power bus layer located above the first transistor layer, a second power bus layer located under the second transistor layer, and a first interconnect layer located above the first power bus layer.

Abstract: Various 3D memory cells, array architectures, and processes are disclosed. In an embodiment, a memory cell structure includes a first semiconductor material, a floating body semiconductor material having an internal side surface that surrounds and connects to the first semiconductor material, and a second semiconductor material having an internal side surface that surrounds and connects to the floating body semiconductor material. The memory cell structure also includes a first dielectric layer connected to a top surface of the floating body material, a second dielectric layer connected to a bottom surface of the floating body material, a front gate connected to the first dielectric layer, and a back gate connected to the second dielectric layer.

Abstract: Methods and apparatus for NAND flash memory are disclosed. In an embodiment, a method is provided for programming a memory device having a plurality of memory chips that comprise multiple-level-cells. The method includes loading first data in a first chip, programming the first data into selected cells of the first chip using a single-level-cell (SLC) programming mode, and reprogramming the first data stored in the selected cells of the first chip to other cells of the first chip using a multiple-level-cell programming mode. The method also includes repeating the operations of loading, programming, and reprogramming for the remaining chips. The loading operations for the remaining chips begin at the completion of the loading operation for the first chip and occur in a non-overlapping sequential manner, and the loading operations for the remaining chips are performed in parallel with the programming and reprogramming operations of the first chip.