Patents by Inventor Fu-Chang Hsu

Fu-Chang Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11567291
    Abstract: An optical system is provided and includes a fixed assembly, a movable element, a movable assembly, a driving module and a stopping assembly. The fixed assembly defines a main axis. The movable element is movable relative to the fixed assembly and is connected to a first optical element. The movable assembly is connected to the movable element. The driving module is configured to drive the movable assembly so as to drive the movable element to move relative to the fixed assembly. The stopping assembly is configured to limit the range of motion of the movable element.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: January 31, 2023
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Che-Wei Chang, Chih-Wen Chiang, Chen-Er Hsu, Fu-Yuan Wu, Shou-Jen Liu, Chih-Wei Weng, Mao-Kuo Hsu, Hsueh-Ju Lu, Che-Hsiang Chiu
  • Publication number: 20230022531
    Abstract: Methods and apparatus for NAND flash memory are disclosed. In an embodiment, a method is provided for programming a memory device having a plurality of memory chips that comprise multiple-level-cells. The method includes loading first data in a first chip, programming the first data into selected cells of the first chip using a single-level-cell (SLC) programming mode, and reprogramming the first data stored in the selected cells of the first chip to other cells of the first chip using a multiple-level-cell programming mode. The method also includes repeating the operations of loading, programming, and reprogramming for the remaining chips. The loading operations for the remaining chips begin at the completion of the loading operation for the first chip and occur in a non-overlapping sequential manner, and the loading operations for the remaining chips are performed in parallel with the programming and reprogramming operations of the first chip.
    Type: Application
    Filed: August 1, 2022
    Publication date: January 26, 2023
    Inventor: Fu-Chang Hsu
  • Patent number: 11555981
    Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a stopping assembly. The fixed assembly has a main axis. The movable assembly is configured to connect an optical element, and the movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The stopping assembly is configured to limit the movement of the movable assembly relative to the fixed assembly within a range of motion.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: January 17, 2023
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Liang-Ting Ho, Chen-Er Hsu, Yi-Liang Chan, Fu-Lai Tseng, Fu-Yuan Wu, Chen-Chi Kuo, Ying-Jen Wang, Wei-Han Hsia, Yi-Hsin Tseng, Wen-Chang Lin, Chun-Chia Liao, Shou-Jen Liu, Chao-Chun Chang, Yi-Chieh Lin, Shang-Yu Hsu, Yu-Huai Liao, Shih-Wei Hung, Sin-Hong Lin, Kun-Shih Lin, Yu-Cheng Lin, Wen-Yen Huang, Wei-Jhe Shen, Chih-Shiang Wu, Sin-Jhong Song, Che-Hsiang Chiu, Sheng-Chang Lin
  • Patent number: 11522016
    Abstract: Three-dimensional vertical memory array cell structures and processes. In an exemplary embodiment, a 3D vertical memory array structure is formed by performing operations that include forming an array stack having alternating metal layers and insulator layers, forming a hole through the array stack to expose internal surfaces of the metal layers and internal surfaces of the insulator layers, and performing a metal-oxidation process on the internal surfaces of the metal layers to form selector devices on the internal surfaces of the metal layers. The operations also include depositing one of resistive material or phase-change material within the hole on the selector devices and the internal surfaces of the insulator layers, such that the hole is reduced to a smaller hole, and depositing conductor material in the smaller hole.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: December 6, 2022
    Inventor: Fu-Chang Hsu
  • Publication number: 20220351790
    Abstract: Methods and apparatus for a novel memory array are disclosed. In an embodiment, a method is provided for reading a dynamic random-access memory (DRAM) array. The method includes activating the bit line select gates to equalize voltage levels on a plurality of bit lines, deactivating the bit line select gates to maintain the equalized voltage levels on the plurality of bit lines using a bit line capacitance associated with each bit line, and activating a selected word line to access selected memory cells connected to the selected word line. The method also includes activating bit line select gates to pass first data from a first bit line and second data from a second bit line to the sense amplifier. The first data is from a selected memory cell and the second data is reference data. The method also includes determining sensed data from the first and second data.
    Type: Application
    Filed: July 15, 2022
    Publication date: November 3, 2022
    Inventor: Fu-Chang Hsu
  • Publication number: 20220296065
    Abstract: A floor types identifying device for use in a vacuum cleaner is disclosed, and comprises a current sensing unit coupled and a processing and controlling module. When a suction head is moved, a driving current of a roller brush driving motor is detected by the current sensing unit, such that the processing and controlling module judges that the suction head is moved on a specific floor that has a hard surface, a short-pile-carpeted surface or a long-pile-carpeted surface according to a variation of the driving current. Therefore, for a vacuum cleaner that is integrated with the floor types identifying device of the present invention, both suction power of the vacuum cleaner and driving power of the roller driving motor can be properly adjusted in response to the floor's surficial material type.
    Type: Application
    Filed: March 11, 2022
    Publication date: September 22, 2022
    Applicant: TALENTONE HONG KONG LIMITED
    Inventors: CHIA-CHANG HSU, Fu-Yuen Fong, Kwok Lit Chan
  • Patent number: 11422357
    Abstract: An optical system is provided and includes a fixed assembly, a movable element and a driving module. The fixed assembly has a main axis. The movable element is movable relative to the fixed assembly, and the movable element is connected to a first optical element. The driving module is configured to drive the movable element to move relative to the fixed assembly.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: August 23, 2022
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Che-Wei Chang, Chih-Wen Chiang, Chen-Er Hsu, Fu-Yuan Wu, Shou-Jen Liu, Chih-Wei Weng, Mao-Kuo Hsu, Hsueh-Ju Lu, Che-Hsiang Chiu
  • Patent number: 11422330
    Abstract: A driving mechanism for moving an optical element is provided, including a movable portion, a fixed portion, a driving assembly, and a first resilient element. The movable portion is for connecting the optical element. The movable portion is movable relative to the fixed portion. The driving assembly drives the movable portion to move relative to the fixed portion. The first resilient element has a board structure. The movable portion is movably connected to the fixed portion via the first resilient element. The fixed portion includes a connection surface, a restricting surface, and a recessed portion. At least a portion of the first resilient element is disposed on the connection surface. The restricting surface contacts and restricts the movable portion. The recessed portion is located between the connection surface and the restricting surface, wherein the recessed portion is lower than the connection surface and the restricting surface.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: August 23, 2022
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Bing-Ru Song, Yi-Ho Chen, Chia-Pin Hsu, Chih-Wei Weng, Shin-Hua Chen, Chien-Lun Huang, Chao-Chun Chang, Shou-Jen Liu, Kun-Shih Lin, Nai-Wen Hsu, Yu-Cheng Lin, Shang-Yu Hsu, Yu-Huai Liao, Yi-Hsin Nieh, Shih-Ting Huang, Kuo-Chun Kao, Fu-Yuan Wu
  • Publication number: 20220164638
    Abstract: Methods and apparatus for neural network arrays are disclosed. In an embodiment, a neural network array includes a plurality of strings, each string having a drain select gate transistor connected to a plurality of non-volatile memory cells that are connected in series and function as synapses, and a plurality of output nodes, each output node connected to receive output signals from a plurality of drain terminals of the drain select gates. The array also includes a plurality of input nodes, each input node connected to provide input signals to a plurality of gate terminals of the drain select gates, and a plurality of weight select signals connected to the plurality of non-volatile memory cells in each string, respectively. Each weight select signal provides a selected voltage to a selected non-volatile memory cell to cause the selected non-volatile memory cell to conduct current according to a selected characteristic of the selected non-volatile memory cell.
    Type: Application
    Filed: November 24, 2021
    Publication date: May 26, 2022
    Inventors: Fu-Chang Hsu, Kevin Hsu
  • Publication number: 20220083836
    Abstract: Configurable three-dimensional neural network array. In an exemplary embodiment, a three-dimensional (3D) neural network array includes a plurality of stacked synapse layers having a first orientation, and a plurality of synapse lines having a second orientation and passing through the synapse layers. The neural network array also includes synapse elements connected between the synapse layers and synapse lines. Each synapse element includes a programmable resistive element. The neural network array also includes a plurality of output neurons, and a plurality of select transistors connected between the synapse lines and the output neurons. The gate terminals of the select transistors receive input signals.
    Type: Application
    Filed: November 22, 2021
    Publication date: March 17, 2022
    Inventors: Fu-Chang Hsu, Kevin Hsu
  • Publication number: 20220044746
    Abstract: Methods and apparatus for memory operations disclosed. In an embodiment, a method is provided for programming multiple-level-cells. The method includes programming data to single-level-cells (SLC) on SLC word lines using SLC programming operations, applying ramp data to the SLC word lines to determine selected ramp data that matches the data stored in (SLC) cells, and programming multiple-level cells to have a voltage threshold level that is associated with the ramp data. In an embodiment, an apparatus includes a first plane having a plurality of first cell strings coupled to a first page buffer. Each first cell string comprises a plurality of multiple-level cells. The apparatus also includes a second plane having a plurality of second cell strings coupled to a second page buffer. Each second cell string comprises a plurality of single-level cells. The apparatus is also configured so that the first page buffer is connected to communicate with the second page buffer.
    Type: Application
    Filed: October 20, 2021
    Publication date: February 10, 2022
    Inventor: Fu-Chang Hsu
  • Publication number: 20220037519
    Abstract: Transistor structures and associated processes are disclosed. In an exemplary embodiment, a transistor structure is provided that includes a conductor layer divided into a plurality of separate conductor regions and a plurality of lateral transistors formed on top of the plurality of separate conductor regions, respectively. Each lateral transistor comprises a source, a drain, and a gate region, and at least one of the source, drain, and gate regions of each lateral transistor is conductively coupled underneath to its respective conductor region.
    Type: Application
    Filed: July 29, 2021
    Publication date: February 3, 2022
    Inventor: Fu-Chang Hsu
  • Publication number: 20220028469
    Abstract: Methods and apparatus for memory operations disclosed. In an embodiment, a method is provided for programming multiple-level cells in a memory array. The memory array includes a plurality of planes and each plane includes a plurality of bit lines. The method includes storing multiple data bits in a first group of planes, one data bit per plane. The multiple data bits are stored in bit line capacitances of the first group of planes. The method also includes programming a selected multiple-level cell in a selected plane according to the multiple data bits that are stored in the bit line capacitances of the first group of planes. The selected plane is not one of the first group of planes.
    Type: Application
    Filed: October 1, 2021
    Publication date: January 27, 2022
    Inventor: Fu-Chang Hsu
  • Patent number: 11232835
    Abstract: Methods and apparatus for reading NAND flash memory are disclosed. In an embodiment, a method is provided for reading a NAND flash memory that includes strings of memory cells that are coupled to bit lines and word lines. The method includes precharging a plurality of bit lines to a precharge voltage level, and applying a sequence of word line voltages to a selected word line. The method also includes initiating discharge of one or more bit lines associated with one or more cells, respectively. The method also includes controlling discharging current of discharging bit lines to achieve identical discharge rates, waiting for a discharging time period for each bit line that is discharging, and latching bit line data at an end of each discharge time period.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: January 25, 2022
    Assignee: NEO Semiconductor, Inc.
    Inventor: Fu-Chang Hsu
  • Patent number: 11205116
    Abstract: Three-dimensional neural network array. In an exemplary embodiment, a three-dimensional (3D) neural network includes a plurality of input conductors forming a plurality of stacked input layers having a first orientation, and at least one output conductor forming an output layer having the first orientation. The three-dimensional (3D) neural network also includes a plurality of hidden conductors having a second orientation. Each hidden conductor includes an in-line threshold element. The three-dimensional (3D) neural network also includes synapse elements coupled between the hidden conductors and the input conductors and between the hidden conductors and the output conductor. Each synapse element includes a programmable resistive element.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: December 21, 2021
    Inventors: Fu-Chang Hsu, Kevin Hsu
  • Publication number: 20210391027
    Abstract: Methods and apparatus for NAND flash memory are disclosed. In an embodiment, a NAND flash memory is provided that includes a plurality of bit lines connected to a plurality of bit line select gates, respectively, and a page buffer connected to the plurality of bit line select gates. The NAND flash memory also includes a plurality of load devices connected to the plurality of bit lines, respectively. The plurality of load devices are configured to provide load current during read operations.
    Type: Application
    Filed: August 26, 2021
    Publication date: December 16, 2021
    Inventor: Fu-Chang Hsu
  • Patent number: 11182664
    Abstract: Configurable three-dimensional neural network array. In an exemplary embodiment, a three-dimensional (3D) neural network array includes a plurality of stacked synapse layers having a first orientation, and a plurality of synapse lines having a second orientation and passing through the synapse layers. The neural network array also includes synapse elements connected between the synapse layers and synapse lines. Each synapse element includes a programmable resistive element. The neural network array also includes a plurality of output neurons, and a plurality of select transistors connected between the synapse lines and the output neurons. The gate terminals of the select transistors receive input signals.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: November 23, 2021
    Inventors: Fu-Chang Hsu, Kevin Hsu
  • Publication number: 20210327519
    Abstract: Methods and apparatus for NAND flash memory are disclosed. In an embodiment, a method is provided for programming a NAND flash memory. The method includes precharging selected bit lines of selected memory cells with a bias voltage level while unselected bit lines maintain the inhibit voltage, applying a verify voltage to a selected word line that is coupled to the selected memory cells, and discharging the selected bit lines that are coupled to on-cells over a first time interval. The method also includes sensing a sensed voltage level on a selected bit line, loading the selected bit line with the inhibit voltage level when the sensed voltage level is above a threshold level and a program voltage when the sensed voltage level is equal to or below the threshold level, and repeating the operations of sensing and loading for each of the selected bit lines.
    Type: Application
    Filed: May 25, 2021
    Publication date: October 21, 2021
    Inventor: Fu-Chang Hsu
  • Publication number: 20210296556
    Abstract: A quantum bit array is disclosed. In an embodiment, the quantum bit array includes a control gate coupled to a qubit and at least one pass gate coupled between the qubit and an adjacent qubit to control operation of the qubit of the quantum bit array, a bit line, and a first transistor channel that connects the bit line to the control gate. The array further comprises at least one word line coupled to the first transistor channel. The at least one word line selectively controls charge flow through the first transistor channel. The array further comprises a capacitor coupled to selectively store charge in the first transistor channel.
    Type: Application
    Filed: March 22, 2021
    Publication date: September 23, 2021
    Inventors: Fu-Chang Hsu, Kevin Hsu
  • Publication number: 20210296360
    Abstract: A three dimensional double-density memory array is disclosed. In an embodiment, a three-dimensional (3D) double density array comprises a string of memory devices that are configured so that a first portion of the memory devices form a first channel and a second portion of the memory devices form a second channel. The array also comprises a plurality of word lines coupled to the string of memory devices. Each word line is coupled to a memory device that forms the first channel and a memory device that forms the second channel. The array also comprises at least one drain select gate that couples the first and second channels to a bit line.
    Type: Application
    Filed: March 22, 2021
    Publication date: September 23, 2021
    Inventor: Fu-Chang Hsu