Patents by Inventor Fu-Change Hsu

Fu-Change Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5748545
    Abstract: A memory device with an on-chip manufacturing and memory cell defect detection capability includes a memory array with a plurality of memory cells that are organized in rows and columns, a plurality of word lines that interconnect respectively the rows of memory cells, and a plurality of bit lines that interconnect respectively the columns of memory cells. Global word line short and global word line open testing circuits are provided to detect the presence of a word line short or word line open condition. Local word line short and local word line open testing circuits are provided to identify the defective word line. Global bit line short and global bit line open testing circuits are provided to detect the presence of a bit line short or bit line open condition. A local bit line short/open testing circuit is used to identify the defective bit line.
    Type: Grant
    Filed: April 3, 1997
    Date of Patent: May 5, 1998
    Assignee: Aplus Integrated Circuits, Inc.
    Inventors: Peter W. Lee, Hsing-Ya Tsao, Fu-Chang Hsu
  • Patent number: 5687121
    Abstract: A flash memory wordline decoder includes a plurality of voltage terminals to receive a plurality of voltages, a plurality of address terminals to receive a plurality of address signals, a procedure terminal to receive a procedure signal, and a plurality of output wordlines adapted to be coupled to a bank of flash transistors. The wordline decoder circuit is configured to decode the address signals and includes latches coupled to the wordlines, where the latches are configured to latch the wordlines and to provide an operational voltage on the wordline to accomplish a predetermined operation responsive to the procedure signal. Advantages of the invention include a verification with a low verification voltage such as 1 V or less for operating with a VDD supply voltage as low as 1.5 V. The decoder also reduces erase/write cycle time and improves expected lifetime of the flash memory due to reduced stress on the flash transistors within the flash memory.
    Type: Grant
    Filed: May 14, 1996
    Date of Patent: November 11, 1997
    Assignee: Aplus Integrated Circuits, Inc.
    Inventors: Peter W. Lee, Hsing-Ya Tsao, Fu-Chang Hsu
  • Patent number: 5682350
    Abstract: A flash memory includes a bank of flash transistors forming a plurality of rows and a plurality of columns, each flash transistor having a gate, drain and source, where the gates of flash transistors in each row are coupled to common wordlines, the drains of flash transistors in each column are coupled to common metal 1 lines divided into even metal 1 lines and odd metal 1 lines and the sources of the flash transistors are coupled to a common sourceline. A set of first selection transistors are coupled between even metal 1 lines and metal 2 lines having a pitch twice that of said metal 1 lines and controlled by a first select signal to selectively couple the even metal 1 lines to the metal 2 lines. A set of second selection transistors are coupled between odd metal 1 lines and the metal 2 lines and controlled by a second select signal to selectively couple the odd metal 1 lines to the metal 2 lines.
    Type: Grant
    Filed: October 7, 1996
    Date of Patent: October 28, 1997
    Assignee: Aplus Integrated Circuits, Inc.
    Inventors: Peter W. Lee, Hsing-Ya Tsao, Fu-Chang Hsu
  • Patent number: 5646890
    Abstract: A flexible word-erase flash memory includes a first bank of flash transistors forming a plurality of rows and a plurality of columns, where the gates of transistors in each row are coupled to common wordlines, the drains of transistors in each column are coupled to common bitlines and the sources of the transistors in the first bank are all coupled to a first sourceline. A second bank of flash transistors form a plurality of rows and a plurality of columns, where the gates of transistors in each row are coupled to common wordlines, the drains of transistors in each column are coupled to common bitlines and the sources of the transistors in the second bank are all coupled to a second sourceline. A wordline decoder is coupled to the wordlines and configured to receive a wordline address signal and to decode the wordline address signal to select a wordline.
    Type: Grant
    Filed: March 29, 1996
    Date of Patent: July 8, 1997
    Assignee: Aplus Integrated Circuits, Inc.
    Inventors: Peter W. Lee, Hsing-Ya Tsao, Fu-Chang Hsu