Patents by Inventor Fu-Cheng Chang

Fu-Cheng Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220318605
    Abstract: A data feature augmentation system and method for a low-precision neural network are provided. The data feature augmentation system includes a first time difference unit. The first time difference unit includes a first sample-and-hold circuit and a subtractor. The first sample-and-hold circuit is used for receiving an input signal and obtaining a first signal according to the input signal. The first signal is related to a first leakage rate of the first sample-and-hold circuit and the first signal is the signal generated by delaying the input signal by one time unit. The subtractor is used for performing subtraction on the input signal and the first signal to obtain a time difference signal. The input signal and the time difference signal are inputted to the low-precision neural network.
    Type: Application
    Filed: July 26, 2021
    Publication date: October 6, 2022
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Fu-Cheng TSAI, Yi-Ching KUO, Chih-Sheng LIN, Shyh-Shyuan SHEU, Tay-Jyi LIN, Shih-Chieh CHANG
  • Publication number: 20220310528
    Abstract: A method of fabricating a semiconductor structure includes forming an alignment mark layer on a substrate; patterning the alignment mark layer for forming at least one alignment mark feature; forming a bottom conductive layer on the patterned alignment mark layer in a substantially conformal manner; forming an insulator layer on the bottom conductive layer; and forming a top conductive layer on the insulator layer.
    Type: Application
    Filed: June 13, 2022
    Publication date: September 29, 2022
    Inventors: Kuo-Hung LEE, Chih-Fei LEE, Fu-Cheng CHANG, Ching-Hung KAO
  • Publication number: 20220300065
    Abstract: The disclosure provides a handheld input device and an electronic system. The handheld input device includes a pen-shaped body, a flexible displacement sensor, and a processor. The flexible displacement sensor is disposed on the pen-shaped body, wherein the flexible displacement sensor deforms in response to a pressing force applied onto the flexible displacement sensor. The processor is coupled to the flexible pressure sensor and disposed in the pen-shaped body, wherein the processor is configured to perform: obtaining a specific displacement of the flexible displacement sensor; determining a stroke size of a representative object in a virtual environment based on the specific displacement of the flexible displacement sensor, wherein the representative object corresponds to the handheld device.
    Type: Application
    Filed: August 26, 2021
    Publication date: September 22, 2022
    Applicant: HTC Corporation
    Inventors: Wei-Jen Chang, Fu-Cheng Fan
  • Publication number: 20220293650
    Abstract: A semiconductor device includes a plurality of isolation structures, wherein each isolation structure of the plurality of isolation structures is spaced from an adjacent isolation structure of the plurality of isolation structures in a first direction. The semiconductor device further includes a gate structure. The gate structure includes a top surface; a first sidewall angled at a non-perpendicular angle with respect to the top surface; and a second sidewall angled with respect to the top surface. The gate structure further includes a first horizontal surface extending between the first sidewall and the second sidewall, wherein the first horizontal surface is parallel to the top surface, and a dimension of the gate structure in a second direction, perpendicular to the first direction, is less than a dimension of each of the plurality of isolation structures in the second direction.
    Type: Application
    Filed: June 2, 2022
    Publication date: September 15, 2022
    Inventors: Chia-Yu WEI, Fu-Cheng CHANG, Hsin-Chi CHEN, Ching-Hung KAO, Chia-Pin CHENG, Kuo-Cheng LEE, Hsun-Ying HUANG, Yen-Liang LIN
  • Patent number: 11380721
    Abstract: A gate structure includes a gate and a first isolation structure having a top surface and a bottom surface. The gate includes a first sidewall adjacent to the first isolation structure, a second sidewall, a first horizontal surface adjacent to a bottom edge of the first sidewall and a bottom edge of the second sidewall, the first horizontal surface being between the top surface of the first isolation structure and the bottom surface of the first isolation structure. The gate also includes a second horizontal surface adjacent to a top edge of the second sidewall. An effective channel width defined by the gate structure includes a height of the second sidewall and a width of the second horizontal surface.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: July 5, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Yu Wei, Fu-Cheng Chang, Hsin-Chi Chen, Ching-Hung Kao, Chia-Pin Cheng, Kuo-Cheng Lee, Hsun-Ying Huang, Yen-Liang Lin
  • Patent number: 11362039
    Abstract: A method of fabricating a semiconductor structure includes forming an alignment mark layer on a substrate; patterning the alignment mark layer for forming at least one alignment mark feature; forming a bottom conductive layer on the patterned alignment mark layer in a substantially conformal manner; forming an insulator layer on the bottom conductive layer; and forming a top conductive layer on the insulator layer.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: June 14, 2022
    Inventors: Kuo-Hung Lee, Chih-Fei Lee, Fu-Cheng Chang, Ching-Hung Kao
  • Publication number: 20210391361
    Abstract: An image sensor device includes a substrate, a deep-trench isolation structure, a buffer layer, and a light blocking structure. The substrate has a photosensitive region. The deep-trench isolation structure is in the substrate and adjacent the photosensitive region. The buffer layer is over the photosensitive region and the deep-trench isolation structure. The light blocking structure is over the buffer layer. A bottom portion of the light blocking structure is embedded in the buffer layer.
    Type: Application
    Filed: June 12, 2020
    Publication date: December 16, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zen-Fong HUANG, Fu-Cheng CHANG
  • Publication number: 20210242080
    Abstract: A method includes bonding a first wafer to a second wafer. The first wafer includes a plurality of dielectric layers, a metal pipe penetrating through the plurality of dielectric layers, and a dielectric region encircled by the metal pipe. The dielectric region has a plurality of steps formed of sidewalls and top surfaces of portions of the plurality of dielectric layers that are encircled by the metal pipe. The method further includes etching the first wafer to remove the dielectric region and to leave an opening encircled by the metal pipe, extending the opening into the second wafer to reveal a metal pad in the second wafer, and filling the opening with a conductive material to form a conductive plug in the opening.
    Type: Application
    Filed: April 23, 2021
    Publication date: August 5, 2021
    Inventors: Ssu-Chiang Weng, Ping-Hao Lin, Fu-Cheng Chang
  • Publication number: 20210183935
    Abstract: Photosensors may be formed on a front side of a semiconductor substrate. An optical refraction layer having a first refractive index may be formed on a backside of the semiconductor substrate. A grid structure including openings is formed over the optical refraction layer. A masking material layer is formed over the grid structure and the optical refraction layer. The masking material layer may be anisotropically etched using an anisotropic etch process that collaterally etches a material of the optical refraction layer and forms non-planar distal surface portions including random protrusions on physically exposed portions of the optical refraction layer. An optically transparent layer having a second refractive index that is different from the first refractive index may be formed on the non-planar distal surface portions of the optical refraction layer. A refractive interface refracts incident light in random directions, and improves quantum efficiency of the photosensors.
    Type: Application
    Filed: December 16, 2019
    Publication date: June 17, 2021
    Inventors: Po-Han CHEN, Kuo-Cheng LEE, Fu-Cheng CHANG
  • Patent number: 11004733
    Abstract: A method includes bonding a first wafer to a second wafer. The first wafer includes a plurality of dielectric layers, a metal pipe penetrating through the plurality of dielectric layers, and a dielectric region encircled by the metal pipe. The dielectric region has a plurality of steps formed of sidewalls and top surfaces of portions of the plurality of dielectric layers that are encircled by the metal pipe. The method further includes etching the first wafer to remove the dielectric region and to leave an opening encircled by the metal pipe, extending the opening into the second wafer to reveal a metal pad in the second wafer, and filling the opening with a conductive material to form a conductive plug in the opening.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ssu-Chiang Weng, Ping-Hao Lin, Fu-Cheng Chang
  • Publication number: 20210028318
    Abstract: A semiconductor device includes a semiconductor substrate, a photo sensing region, and a plurality of nanostructures. The semiconductor substrate has a first dopant. The photo sensing region is embedded in the semiconductor substrate, has a top surface level with a top surface of the semiconductor substrate, and has a second dopant that is of a different conductivity type than the first dopant. The plurality of nanostructures is on the photo sensing region and is made of a material the same as the photo sensing region.
    Type: Application
    Filed: October 9, 2020
    Publication date: January 28, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Hsiang TSENG, Chih-Fei LEE, Chia-Pin CHENG, Fu-Cheng CHANG
  • Publication number: 20210028120
    Abstract: A method of fabricating a semiconductor structure includes forming an alignment mark layer on a substrate; patterning the alignment mark layer for forming at least one alignment mark feature; forming a bottom conductive layer on the patterned alignment mark layer in a substantially conformal manner; forming an insulator layer on the bottom conductive layer; and forming a top conductive layer on the insulator layer.
    Type: Application
    Filed: October 12, 2020
    Publication date: January 28, 2021
    Inventors: Kuo-Hung LEE, Chih-Fei LEE, Fu-Cheng CHANG, Ching-Hung KAO
  • Patent number: 10804414
    Abstract: A method of forming a semiconductor device includes forming a photo sensing region in a semiconductor substrate, wherein the semiconductor substrate is of a first type dopant and the photo sensing region is of a second type dopant that has a different conductivity type than the first type dopant; forming a nanostructure layer in contact with an interface between the photo sensing region and the semiconductor substrate; and etching the nanostructure layer until exposing the photo sensing region to form a plurality of nanostructures.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: October 13, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Hsiang Tseng, Chih-Fei Lee, Chia-Pin Cheng, Fu-Cheng Chang
  • Patent number: 10804211
    Abstract: A method of fabricating a semiconductor structure includes forming an alignment mark layer on a substrate; patterning the alignment mark layer for forming at least one alignment mark feature; forming a bottom conductive layer on the patterned alignment mark layer in a substantially conformal manner; forming an insulator layer on the bottom conductive layer; and forming a top conductive layer on the insulator layer.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: October 13, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Kuo-Hung Lee, Chih-Fei Lee, Fu-Cheng Chang, Ching-Hung Kao
  • Publication number: 20200185440
    Abstract: A gate structure includes a gate and a first isolation structure having a top surface and a bottom surface. The gate includes a first sidewall adjacent to the first isolation structure, a second sidewall, a first horizontal surface adjacent to a bottom edge of the first sidewall and a bottom edge of the second sidewall, the first horizontal surface being between the top surface of the first isolation structure and the bottom surface of the first isolation structure. The gate also includes a second horizontal surface adjacent to a top edge of the second sidewall. An effective channel width defined by the gate structure includes a height of the second sidewall and a width of the second horizontal surface.
    Type: Application
    Filed: February 13, 2020
    Publication date: June 11, 2020
    Inventors: Chia-Yu WEI, Fu-Cheng CHANG, Hsin-Chi CHEN, Ching-Hung KAO, Chia-Pin CHENG, Kuo-Cheng LEE, Hsun-Ying HUANG, Yen-Liang LIN
  • Publication number: 20200135785
    Abstract: An image sensor includes a substrate and a first photodiode (PD) having a first size in the substrate. The image sensor further includes a second PD having a second size in the substrate, wherein the first size is different from the second size. The image sensor further includes a first buffer layer over the substrate. The image sensor further includes a shield layer over the first buffer, wherein the first buffer layer and the shield layer define a first recess aligned with the first PD and a second recess aligned with the second PD. The image sensor further includes a flicker reduction layer in the first recess, wherein the second recess is free of the flicker reduction layer.
    Type: Application
    Filed: October 7, 2019
    Publication date: April 30, 2020
    Inventors: Po-Han CHEN, Chen-Chun CHEN, Fu-Cheng CHANG, Kuo-Cheng LEE
  • Patent number: 10566361
    Abstract: A gate structure includes a gate and a first isolation structure having a top surface and a bottom surface. The gate includes a first sidewall adjacent to the first isolation structure, a second sidewall, a first horizontal surface adjacent to a bottom edge of the first sidewall and a bottom edge of the second sidewall, the first horizontal surface being between the top surface of the first isolation structure and the bottom surface of the first isolation structure. The gate also includes a second horizontal surface adjacent to a top edge of the second sidewall. An effective channel width defined by the gate structure includes a height of the second sidewall and a width of the second horizontal surface.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: February 18, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Yu Wei, Fu-Cheng Chang, Hsin-Chi Chen, Ching-Hung Kao, Chia-Pin Cheng, Kuo-Cheng Lee, Hsun-Ying Huang, Yen-Liang Lin
  • Publication number: 20200006128
    Abstract: A method includes bonding a first wafer to a second wafer. The first wafer includes a plurality of dielectric layers, a metal pipe penetrating through the plurality of dielectric layers, and a dielectric region encircled by the metal pipe. The dielectric region has a plurality of steps formed of sidewalls and top surfaces of portions of the plurality of dielectric layers that are encircled by the metal pipe. The method further includes etching the first wafer to remove the dielectric region and to leave an opening encircled by the metal pipe, extending the opening into the second wafer to reveal a metal pad in the second wafer, and filling the opening with a conductive material to form a conductive plug in the opening.
    Type: Application
    Filed: April 30, 2019
    Publication date: January 2, 2020
    Inventors: Ssu-Chiang Weng, Ping-Hao Lin, Fu-Cheng Chang
  • Publication number: 20190252559
    Abstract: A method of forming a semiconductor device includes forming a photo sensing region in a semiconductor substrate, wherein the semiconductor substrate is of a first type dopant and the photo sensing region is of a second type dopant that has a different conductivity type than the first type dopant; forming a nanostructure layer in contact with an interface between the photo sensing region and the semiconductor substrate; and etching the nanostructure layer until exposing the photo sensing region to form a plurality of nanostructures.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 15, 2019
    Inventors: Hsin-Hsiang Tseng, Chih-Fei Lee, Chia-Pin Cheng, Fu-Cheng Chang
  • Publication number: 20190148146
    Abstract: A method of forming a semiconductor structure is disclosed. A multi-layer structure is formed over a substrate. A photoresist stack with a stepped sidewall is formed on the multi-layer structure. A pattern of the photoresist stack is transferred to the multi-layer structure.
    Type: Application
    Filed: October 30, 2018
    Publication date: May 16, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ping-Hao Lin, Fu-Cheng Chang