Abstract: A data feature augmentation system and method for a low-precision neural network are provided. The data feature augmentation system includes a first time difference unit. The first time difference unit includes a first sample-and-hold circuit and a subtractor. The first sample-and-hold circuit is used for receiving an input signal and obtaining a first signal according to the input signal. The first signal is related to a first leakage rate of the first sample-and-hold circuit and the first signal is the signal generated by delaying the input signal by one time unit. The subtractor is used for performing subtraction on the input signal and the first signal to obtain a time difference signal. The input signal and the time difference signal are inputted to the low-precision neural network.

Abstract: A method of fabricating a semiconductor structure includes forming an alignment mark layer on a substrate; patterning the alignment mark layer for forming at least one alignment mark feature; forming a bottom conductive layer on the patterned alignment mark layer in a substantially conformal manner; forming an insulator layer on the bottom conductive layer; and forming a top conductive layer on the insulator layer.

Abstract: The disclosure provides a handheld input device and an electronic system. The handheld input device includes a pen-shaped body, a flexible displacement sensor, and a processor. The flexible displacement sensor is disposed on the pen-shaped body, wherein the flexible displacement sensor deforms in response to a pressing force applied onto the flexible displacement sensor. The processor is coupled to the flexible pressure sensor and disposed in the pen-shaped body, wherein the processor is configured to perform: obtaining a specific displacement of the flexible displacement sensor; determining a stroke size of a representative object in a virtual environment based on the specific displacement of the flexible displacement sensor, wherein the representative object corresponds to the handheld device.

Abstract: A semiconductor device includes a plurality of isolation structures, wherein each isolation structure of the plurality of isolation structures is spaced from an adjacent isolation structure of the plurality of isolation structures in a first direction. The semiconductor device further includes a gate structure. The gate structure includes a top surface; a first sidewall angled at a non-perpendicular angle with respect to the top surface; and a second sidewall angled with respect to the top surface. The gate structure further includes a first horizontal surface extending between the first sidewall and the second sidewall, wherein the first horizontal surface is parallel to the top surface, and a dimension of the gate structure in a second direction, perpendicular to the first direction, is less than a dimension of each of the plurality of isolation structures in the second direction.

Abstract: A gate structure includes a gate and a first isolation structure having a top surface and a bottom surface. The gate includes a first sidewall adjacent to the first isolation structure, a second sidewall, a first horizontal surface adjacent to a bottom edge of the first sidewall and a bottom edge of the second sidewall, the first horizontal surface being between the top surface of the first isolation structure and the bottom surface of the first isolation structure. The gate also includes a second horizontal surface adjacent to a top edge of the second sidewall. An effective channel width defined by the gate structure includes a height of the second sidewall and a width of the second horizontal surface.

Abstract: A method of fabricating a semiconductor structure includes forming an alignment mark layer on a substrate; patterning the alignment mark layer for forming at least one alignment mark feature; forming a bottom conductive layer on the patterned alignment mark layer in a substantially conformal manner; forming an insulator layer on the bottom conductive layer; and forming a top conductive layer on the insulator layer.

Abstract: An image sensor device includes a substrate, a deep-trench isolation structure, a buffer layer, and a light blocking structure. The substrate has a photosensitive region. The deep-trench isolation structure is in the substrate and adjacent the photosensitive region. The buffer layer is over the photosensitive region and the deep-trench isolation structure. The light blocking structure is over the buffer layer. A bottom portion of the light blocking structure is embedded in the buffer layer.

Abstract: A method includes bonding a first wafer to a second wafer. The first wafer includes a plurality of dielectric layers, a metal pipe penetrating through the plurality of dielectric layers, and a dielectric region encircled by the metal pipe. The dielectric region has a plurality of steps formed of sidewalls and top surfaces of portions of the plurality of dielectric layers that are encircled by the metal pipe. The method further includes etching the first wafer to remove the dielectric region and to leave an opening encircled by the metal pipe, extending the opening into the second wafer to reveal a metal pad in the second wafer, and filling the opening with a conductive material to form a conductive plug in the opening.

Abstract: Photosensors may be formed on a front side of a semiconductor substrate. An optical refraction layer having a first refractive index may be formed on a backside of the semiconductor substrate. A grid structure including openings is formed over the optical refraction layer. A masking material layer is formed over the grid structure and the optical refraction layer. The masking material layer may be anisotropically etched using an anisotropic etch process that collaterally etches a material of the optical refraction layer and forms non-planar distal surface portions including random protrusions on physically exposed portions of the optical refraction layer. An optically transparent layer having a second refractive index that is different from the first refractive index may be formed on the non-planar distal surface portions of the optical refraction layer. A refractive interface refracts incident light in random directions, and improves quantum efficiency of the photosensors.

Abstract: A method includes bonding a first wafer to a second wafer. The first wafer includes a plurality of dielectric layers, a metal pipe penetrating through the plurality of dielectric layers, and a dielectric region encircled by the metal pipe. The dielectric region has a plurality of steps formed of sidewalls and top surfaces of portions of the plurality of dielectric layers that are encircled by the metal pipe. The method further includes etching the first wafer to remove the dielectric region and to leave an opening encircled by the metal pipe, extending the opening into the second wafer to reveal a metal pad in the second wafer, and filling the opening with a conductive material to form a conductive plug in the opening.

Abstract: A semiconductor device includes a semiconductor substrate, a photo sensing region, and a plurality of nanostructures. The semiconductor substrate has a first dopant. The photo sensing region is embedded in the semiconductor substrate, has a top surface level with a top surface of the semiconductor substrate, and has a second dopant that is of a different conductivity type than the first dopant. The plurality of nanostructures is on the photo sensing region and is made of a material the same as the photo sensing region.

Abstract: A method of fabricating a semiconductor structure includes forming an alignment mark layer on a substrate; patterning the alignment mark layer for forming at least one alignment mark feature; forming a bottom conductive layer on the patterned alignment mark layer in a substantially conformal manner; forming an insulator layer on the bottom conductive layer; and forming a top conductive layer on the insulator layer.

Abstract: A method of forming a semiconductor device includes forming a photo sensing region in a semiconductor substrate, wherein the semiconductor substrate is of a first type dopant and the photo sensing region is of a second type dopant that has a different conductivity type than the first type dopant; forming a nanostructure layer in contact with an interface between the photo sensing region and the semiconductor substrate; and etching the nanostructure layer until exposing the photo sensing region to form a plurality of nanostructures.

Abstract: A method of fabricating a semiconductor structure includes forming an alignment mark layer on a substrate; patterning the alignment mark layer for forming at least one alignment mark feature; forming a bottom conductive layer on the patterned alignment mark layer in a substantially conformal manner; forming an insulator layer on the bottom conductive layer; and forming a top conductive layer on the insulator layer.

Abstract: A gate structure includes a gate and a first isolation structure having a top surface and a bottom surface. The gate includes a first sidewall adjacent to the first isolation structure, a second sidewall, a first horizontal surface adjacent to a bottom edge of the first sidewall and a bottom edge of the second sidewall, the first horizontal surface being between the top surface of the first isolation structure and the bottom surface of the first isolation structure. The gate also includes a second horizontal surface adjacent to a top edge of the second sidewall. An effective channel width defined by the gate structure includes a height of the second sidewall and a width of the second horizontal surface.

Abstract: An image sensor includes a substrate and a first photodiode (PD) having a first size in the substrate. The image sensor further includes a second PD having a second size in the substrate, wherein the first size is different from the second size. The image sensor further includes a first buffer layer over the substrate. The image sensor further includes a shield layer over the first buffer, wherein the first buffer layer and the shield layer define a first recess aligned with the first PD and a second recess aligned with the second PD. The image sensor further includes a flicker reduction layer in the first recess, wherein the second recess is free of the flicker reduction layer.

Abstract: A gate structure includes a gate and a first isolation structure having a top surface and a bottom surface. The gate includes a first sidewall adjacent to the first isolation structure, a second sidewall, a first horizontal surface adjacent to a bottom edge of the first sidewall and a bottom edge of the second sidewall, the first horizontal surface being between the top surface of the first isolation structure and the bottom surface of the first isolation structure. The gate also includes a second horizontal surface adjacent to a top edge of the second sidewall. An effective channel width defined by the gate structure includes a height of the second sidewall and a width of the second horizontal surface.

Abstract: A method includes bonding a first wafer to a second wafer. The first wafer includes a plurality of dielectric layers, a metal pipe penetrating through the plurality of dielectric layers, and a dielectric region encircled by the metal pipe. The dielectric region has a plurality of steps formed of sidewalls and top surfaces of portions of the plurality of dielectric layers that are encircled by the metal pipe. The method further includes etching the first wafer to remove the dielectric region and to leave an opening encircled by the metal pipe, extending the opening into the second wafer to reveal a metal pad in the second wafer, and filling the opening with a conductive material to form a conductive plug in the opening.

Abstract: A method of forming a semiconductor device includes forming a photo sensing region in a semiconductor substrate, wherein the semiconductor substrate is of a first type dopant and the photo sensing region is of a second type dopant that has a different conductivity type than the first type dopant; forming a nanostructure layer in contact with an interface between the photo sensing region and the semiconductor substrate; and etching the nanostructure layer until exposing the photo sensing region to form a plurality of nanostructures.

Abstract: A method of forming a semiconductor structure is disclosed. A multi-layer structure is formed over a substrate. A photoresist stack with a stepped sidewall is formed on the multi-layer structure. A pattern of the photoresist stack is transferred to the multi-layer structure.