Patents by Inventor Fu-Cheng Chang
Fu-Cheng Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250142883Abstract: A semiconductor device includes two source/drain regions, two isolation elements, a channel feature, at least one semiconductor layer and a gate feature. The source/drain regions are spaced apart from each other, and are respectively disposed above the isolation elements. The channel feature includes at least one effective channel layer and at least one dummy channel layer that are spaced apart from each other. Each of the at least one effective channel layer extends between the source/drain regions. Each of the at least one dummy channel layer extends between the isolation elements. The at least one semiconductor layer at least covers a lower surface of a bottommost one of the at least one dummy channel layer. The gate feature is disposed around the at least one effective channel layer, such that two opposite surfaces of each of the at least one effective channel layer are adjacent to the gate feature.Type: ApplicationFiled: November 1, 2023Publication date: May 1, 2025Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jung-Hung CHANG, Tsung-Han CHUANG, Fu-Cheng CHANG, Shih-Cheng CHEN, Chia-Cheng TSAI, Kuo-Cheng CHIANG, Chih-Hao WANG
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Publication number: 20250098219Abstract: A device includes: a substrate having a semiconductor fin; a stack of semiconductor channels on the substrate and positioned over the fin; a gate structure wrapping around the semiconductor channels; a source/drain abutting the semiconductor channels; an inner spacer positioned between the stack of semiconductor channels and the fin; an undoped semiconductor layer vertically adjacent the source/drain and laterally adjacent the fin; and an isolation structure that laterally surrounds the undoped semiconductor layer, the isolation structure being between the source/drain and the inner spacer.Type: ApplicationFiled: February 15, 2024Publication date: March 20, 2025Inventors: Jung-Hung CHANG, Shih-Cheng CHEN, Tsung-Han CHUANG, Fu-Cheng CHANG, Wen-Ting LAN, Chia-Cheng TSAI, Kuo-Cheng CHIANG, Chih-Hao WANG, Wang-Chun Huang, Shi-Syuan Huang
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Patent number: 12243772Abstract: A method includes bonding a first wafer to a second wafer. The first wafer includes a plurality of dielectric layers, a metal pipe penetrating through the plurality of dielectric layers, and a dielectric region encircled by the metal pipe. The dielectric region has a plurality of steps formed of sidewalls and top surfaces of portions of the plurality of dielectric layers that are encircled by the metal pipe. The method further includes etching the first wafer to remove the dielectric region and to leave an opening encircled by the metal pipe, extending the opening into the second wafer to reveal a metal pad in the second wafer, and filling the opening with a conductive material to form a conductive plug in the opening.Type: GrantFiled: July 21, 2023Date of Patent: March 4, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ssu-Chiang Weng, Ping-Hao Lin, Fu-Cheng Chang
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Publication number: 20250048764Abstract: An image sensor includes a substrate. The image sensor includes a first photodiode (PD) having a first size in the substrate. The image sensor further includes a second PD having a second size in the substrate, wherein the first size is different from the second size. The image sensor further includes a first layer, wherein the first layer comprises a metal material or a dielectric material, and the first layer defines sidewalls of a first recess aligned with the first PD. The image sensor further includes a second layer in the first recess, wherein a portion of the first layer aligned with the second PD is free of the second layer, and the second layer overhangs the first layer.Type: ApplicationFiled: October 22, 2024Publication date: February 6, 2025Inventors: Po-Han CHEN, Chen-Chu CHEN, Fu-Cheng CHANG, Kuo-Cheng LEE
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Publication number: 20240379704Abstract: Photosensors may be formed on a front side of a semiconductor substrate. An optical refraction layer having a first refractive index may be formed on a backside of the semiconductor substrate. A grid structure including openings is formed over the optical refraction layer. A masking material layer is formed over the grid structure and the optical refraction layer. The masking material layer may be anisotropically etched using an anisotropic etch process that collaterally etches a material of the optical refraction layer and forms non-planar distal surface portions including random protrusions on physically exposed portions of the optical refraction layer. An optically transparent layer having a second refractive index that is different from the first refractive index may be formed on the non-planar distal surface portions of the optical refraction layer. A refractive interface refracts incident light in random directions, and improves quantum efficiency of the photosensors.Type: ApplicationFiled: July 22, 2024Publication date: November 14, 2024Inventors: Po-Han CHEN, Kuo-Cheng LEE, Fu-Cheng CHANG
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Patent number: 12125864Abstract: A method of making an image sensor includes depositing a shield layer over a substrate, wherein the substrate comprises a first photodiode (PD) and a second PD. The method further includes etching the shield layer to define a first recess aligned with the first PD and a second recess aligned with the second PD. The method further includes depositing a flicker reduction layer in the first recess and in the second recess. The method further includes etching the flicker reduction layer to remove the flicker reduction layer from the first recess.Type: GrantFiled: May 17, 2023Date of Patent: October 22, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po-Han Chen, Chen-Chun Chen, Fu-Cheng Chang, Kuo-Cheng Lee
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Patent number: 12107104Abstract: Photosensors may be formed on a front side of a semiconductor substrate. An optical refraction layer having a first refractive index may be formed on a backside of the semiconductor substrate. A grid structure including openings is formed over the optical refraction layer. A masking material layer is formed over the grid structure and the optical refraction layer. The masking material layer may be anisotropically etched using an anisotropic etch process that collaterally etches a material of the optical refraction layer and forms non-planar distal surface portions including random protrusions on physically exposed portions of the optical refraction layer. An optically transparent layer having a second refractive index that is different from the first refractive index may be formed on the non-planar distal surface portions of the optical refraction layer. A refractive interface refracts incident light in random directions, and improves quantum efficiency of the photo sensors.Type: GrantFiled: July 18, 2022Date of Patent: October 1, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Po-Han Chen, Kuo-Cheng Lee, Fu-Cheng Chang
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Publication number: 20240282838Abstract: A device includes: a stack of nanostructures; a gate structure that wraps around the nanostructures; an isolation region between the stack of nanostructures and another stack of nanostructures adjacent thereto along a first direction; a source/drain region that abuts at least one of the nanostructures; and a spacer layer that is on sidewalls of the gate structure and on sidewalls of the source/drain region, the spacer layer covering an area between the source/drain region and a neighboring source/drain region of another transistor along the first direction.Type: ApplicationFiled: June 28, 2023Publication date: August 22, 2024Inventors: Jung-Hung CHANG, Tsung-Han CHUANG, Fu-Cheng CHANG, Shih-Cheng CHEN, Chia-Cheng TSAI, Kuo-Cheng CHIANG
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Patent number: 11901305Abstract: A method of fabricating a semiconductor structure includes forming an alignment mark layer on a substrate; patterning the alignment mark layer for forming at least one alignment mark feature; forming a bottom conductive layer on the patterned alignment mark layer in a substantially conformal manner; forming an insulator layer on the bottom conductive layer; and forming a top conductive layer on the insulator layer.Type: GrantFiled: June 13, 2022Date of Patent: February 13, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.Inventors: Kuo-Hung Lee, Chih-Fei Lee, Fu-Cheng Chang, Ching-Hung Kao
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Publication number: 20240038719Abstract: A method of forming a semiconductor structure is provided. Two wafers are first bonded by oxide bonding. Next, the thickness of a first wafer is reduced using an ion implantation and separation approach, and a second wafer is thinned by using a removal process. First devices are formed on the first wafer, and a carrier is then attached over the first wafer, and an alignment process is performed from the bottom of the second wafer to align active regions of the second wafer for placement of the second devices with active regions of the first wafer for placement of the first devices. The second devices are then formed in the active regions of the second wafer. Furthermore, a via structure is formed through the first wafer, the second wafer and the insulation layer therebetween to connect the first and second devices on the two sides of the insulation layer.Type: ApplicationFiled: July 29, 2022Publication date: February 1, 2024Inventors: Wen-Ting LAN, I-Han HUANG, Fu-Cheng CHANG, Lin-Yu HUANG, Shi-Ning JU, Kuo-Cheng CHIANG
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Publication number: 20240021469Abstract: A method includes bonding a first wafer to a second wafer. The first wafer includes a plurality of dielectric layers, a metal pipe penetrating through the plurality of dielectric layers, and a dielectric region encircled by the metal pipe. The dielectric region has a plurality of steps formed of sidewalls and top surfaces of portions of the plurality of dielectric layers that are encircled by the metal pipe. The method further includes etching the first wafer to remove the dielectric region and to leave an opening encircled by the metal pipe, extending the opening into the second wafer to reveal a metal pad in the second wafer, and filling the opening with a conductive material to form a conductive plug in the opening.Type: ApplicationFiled: July 21, 2023Publication date: January 18, 2024Inventors: Ssu-Chiang Weng, Ping-Hao Lin, Fu-Cheng Chang
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Publication number: 20230402405Abstract: The present disclosure describes a method to form a semiconductor structure having an oxide structure on a wafer edge. The method includes forming a device layer on a first substrate, forming an interconnect layer on the device layer, forming an oxide structure on a top surface and along a sidewall surface of the interconnect layer, forming a bonding layer on the oxide structure and the interconnect layer, and bonding the device layer to a second substrate with the bonding layer.Type: ApplicationFiled: March 20, 2023Publication date: December 14, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: I-Han Huang, Fu-Cheng Chang, Wen-Ting Lan, Shi Ning Ju, Lin-Yu Huang, Kuo-Cheng Chiang
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Publication number: 20230378205Abstract: A semiconductor device includes a plurality of isolation structures, wherein each isolation structure of the plurality of isolation structures is spaced from an adjacent isolation structure of the plurality of isolation structures. The semiconductor device further includes a gate structure. The gate structure includes a first sidewall and a second sidewall angled with respect to the first sidewall. The gate structure further includes a first surface extending between the first sidewall and the second sidewall, wherein a dimension of the gate structure in a first direction is less than a dimension of each of the plurality of isolation structures in the first direction.Type: ApplicationFiled: July 31, 2023Publication date: November 23, 2023Inventors: Chia-Yu WEI, Fu-Cheng CHANG, Hsin-Chi CHEN, Ching-Hung KAO, Chia-Pin CHENG, Kuo-Cheng LEE, Hsun-Ying HUANG, Yen-Liang LIN
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Publication number: 20230369517Abstract: An image sensor device includes nanostructures for improving light absorption efficiency. The image sensor device includes a substrate, a light absorption region, and a nanostructure array. The light absorption region is over the substrate. The nanostructure array us over the light absorption region. The nanostructure array includes a plurality of nanostructures repeatedly arranged from a top view.Type: ApplicationFiled: July 26, 2023Publication date: November 16, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Hsiang TSENG, Chih-Fei LEE, Chia-Pin CHENG, Fu-Cheng CHANG
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Patent number: 11791205Abstract: A method includes bonding a first wafer to a second wafer. The first wafer includes a plurality of dielectric layers, a metal pipe penetrating through the plurality of dielectric layers, and a dielectric region encircled by the metal pipe. The dielectric region has a plurality of steps formed of sidewalls and top surfaces of portions of the plurality of dielectric layers that are encircled by the metal pipe. The method further includes etching the first wafer to remove the dielectric region and to leave an opening encircled by the metal pipe, extending the opening into the second wafer to reveal a metal pad in the second wafer, and filling the opening with a conductive material to form a conductive plug in the opening.Type: GrantFiled: April 23, 2021Date of Patent: October 17, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ssu-Chiang Weng, Ping-Hao Lin, Fu-Cheng Chang
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Patent number: 11784198Abstract: A semiconductor device includes a plurality of isolation structures, wherein each isolation structure of the plurality of isolation structures is spaced from an adjacent isolation structure of the plurality of isolation structures in a first direction. The semiconductor device further includes a gate structure. The gate structure includes a top surface; a first sidewall angled at a non-perpendicular angle with respect to the top surface; and a second sidewall angled with respect to the top surface. The gate structure further includes a first horizontal surface extending between the first sidewall and the second sidewall, wherein the first horizontal surface is parallel to the top surface, and a dimension of the gate structure in a second direction, perpendicular to the first direction, is less than a dimension of each of the plurality of isolation structures in the second direction.Type: GrantFiled: June 2, 2022Date of Patent: October 10, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Yu Wei, Fu-Cheng Chang, Hsin-Chi Chen, Ching-Hung Kao, Chia-Pin Cheng, Kuo-Cheng Lee, Hsun-Ying Huang, Yen-Liang Lin
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Patent number: 11777040Abstract: A semiconductor device includes a substrate, a photo sensing region, and a plurality of semiconductor plugs. The photo sensing region is in the substrate. The photo sensing region forms a p-n junction with the substrate. The semiconductor plugs extend from above the photo sensing region into the photo sensing region.Type: GrantFiled: November 28, 2022Date of Patent: October 3, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Hsiang Tseng, Chih-Fei Lee, Chia-Pin Cheng, Fu-Cheng Chang
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Publication number: 20230299104Abstract: A method of making an image sensor includes depositing a shield layer over a substrate, wherein the substrate comprises a first photodiode (PD) and a second PD. The method further includes etching the shield layer to define a first recess aligned with the first PD and a second recess aligned with the second PD. The method further includes depositing a flicker reduction layer in the first recess and in the second recess. The method further includes etching the flicker reduction layer to remove the flicker reduction layer from the first recess.Type: ApplicationFiled: May 17, 2023Publication date: September 21, 2023Inventors: Po-Han CHEN, Chen-Chun CHEN, Fu-Cheng CHANG, Kuo-Cheng LEE
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Patent number: 11764062Abstract: A method of forming a semiconductor structure is disclosed. A multi-layer structure is formed over a substrate. A photoresist stack with a stepped sidewall is formed on the multi-layer structure. A pattern of the photoresist stack is transferred to the multi-layer structure.Type: GrantFiled: October 30, 2018Date of Patent: September 19, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ping-Hao Lin, Fu-Cheng Chang
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Publication number: 20230261023Abstract: An image sensor device includes a substrate, a deep-trench isolation structure, an oxide layer, a light blocking structure, and an adhesion layer. The substrate has a photosensitive region. The deep-trench isolation structure is in the substrate and adjacent the photosensitive region. The oxide layer is over the photosensitive region and the deep-trench isolation structure. The light blocking structure is over the oxide layer. A bottom portion of the light blocking structure is embedded in the oxide layer. The adhesion layer is between the light blocking structure and the oxide layer. The adhesion layer extends beyond a sidewall of a top portion of the light blocking structure.Type: ApplicationFiled: April 21, 2023Publication date: August 17, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Zen-Fong HUANG, Fu-Cheng CHANG