Patents by Inventor Fu-Cheng TSAI
Fu-Cheng TSAI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230153375Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, a third semiconductor element, and a fourth semiconductor element. A first terminal of the first semiconductor element receives a bias voltage. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to a first data node in the memory cell circuit. A second terminal of the third semiconductor element is adapted to receive a reference voltage. A control terminal of the third semiconductor element receives an inverted signal of the computing word-line. A first terminal of the fourth semiconductor element is coupled to a first computing bit-line. A second terminal of the fourth semiconductor element is coupled to a second computing bit-line.Type: ApplicationFiled: January 18, 2023Publication date: May 18, 2023Applicant: Industrial Technology Research InstituteInventors: Chih-Sheng Lin, Jian-Wei Su, Tuo-Hung Hou, Sih-Han Li, Fu-Cheng Tsai, Yu-Hui Lin
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Patent number: 11599600Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, and a third semiconductor element. A first terminal of the first semiconductor element is coupled to a first computing bit-line. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to the memory cell circuit. A first terminal of the second semiconductor element is coupled to a second terminal of the first semiconductor element. A first terminal of the third semiconductor element is coupled to a second terminal of the second semiconductor element. A second terminal of the third semiconductor element is coupled to a second computing bit-line. A control terminal of the third semiconductor element receives a bias voltage.Type: GrantFiled: September 6, 2020Date of Patent: March 7, 2023Assignee: Industrial Technology Research InstituteInventors: Chih-Sheng Lin, Jian-Wei Su, Tuo-Hung Hou, Sih-Han Li, Fu-Cheng Tsai, Yu-Hui Lin
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Publication number: 20220318605Abstract: A data feature augmentation system and method for a low-precision neural network are provided. The data feature augmentation system includes a first time difference unit. The first time difference unit includes a first sample-and-hold circuit and a subtractor. The first sample-and-hold circuit is used for receiving an input signal and obtaining a first signal according to the input signal. The first signal is related to a first leakage rate of the first sample-and-hold circuit and the first signal is the signal generated by delaying the input signal by one time unit. The subtractor is used for performing subtraction on the input signal and the first signal to obtain a time difference signal. The input signal and the time difference signal are inputted to the low-precision neural network.Type: ApplicationFiled: July 26, 2021Publication date: October 6, 2022Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Fu-Cheng TSAI, Yi-Ching KUO, Chih-Sheng LIN, Shyh-Shyuan SHEU, Tay-Jyi LIN, Shih-Chieh CHANG
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Publication number: 20210397675Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, and a third semiconductor element. A first terminal of the first semiconductor element is coupled to a first computing bit-line. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to the memory cell circuit. A first terminal of the second semiconductor element is coupled to a second terminal of the first semiconductor element. A first terminal of the third semiconductor element is coupled to a second terminal of the second semiconductor element. A second terminal of the third semiconductor element is coupled to a second computing bit-line. A control terminal of the third semiconductor element receives a bias voltage.Type: ApplicationFiled: September 6, 2020Publication date: December 23, 2021Applicant: Industrial Technology Research InstituteInventors: Chih-Sheng Lin, Jian-Wei Su, Tuo-Hung Hou, Sih-Han Li, Fu-Cheng Tsai, Yu-Hui Lin
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Patent number: 11145356Abstract: A computation operator in memory and an operation method thereof are provided. The computation operator in memory includes a word line calculator, a decision-maker and a sense amplifier. The word line calculator calculates a number of enabled word lines of a memory. The decision-maker generates a plurality of reference signals according to at least one of the number of enabled word lines and a used size of the memory, the reference signals are configured to set a distribution range. The sense amplifier receives a readout signal of the memory, and obtains a computation result by converting the readout signal according to the reference signals.Type: GrantFiled: April 16, 2020Date of Patent: October 12, 2021Assignee: Industrial Technology Research InstituteInventors: Fu-Cheng Tsai, Heng-Yuan Lee, Chih-Sheng Lin, Jian-Wei Su, Tuo-Hung Hou
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Publication number: 20210257017Abstract: A computation operator in memory and an operation method thereof are provided. The computation operator in memory includes a word line calculator, a decision-maker and a sense amplifier. The word line calculator calculates a number of enabled word lines of a memory. The decision-maker generates a plurality of reference signals according to at least one of the number of enabled word lines and a used size of the memory, the reference signals are configured to set a distribution range. The sense amplifier receives a readout signal of the memory, and obtains a computation result by converting the readout signal according to the reference signals.Type: ApplicationFiled: April 16, 2020Publication date: August 19, 2021Applicant: Industrial Technology Research InstituteInventors: Fu-Cheng Tsai, Heng-Yuan Lee, Chih-Sheng Lin, Jian-Wei Su, Tuo-Hung Hou
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Publication number: 20210192327Abstract: An apparatus and a method for neural network computation are provided. The apparatus for neural network computation includes a first neuron circuit and a second neuron circuit. The first neuron circuit is configured to execute a neural network computation of at least one computing layer with a fixed feature pattern in a neural network algorithm. The second neuron circuit is configured to execute the neural network computation of at least one computing layer with an unfixed feature pattern in the neural network algorithm. The performance of the first neuron circuit is greater than that of the second neuron circuit.Type: ApplicationFiled: December 23, 2020Publication date: June 24, 2021Applicant: Industrial Technology Research InstituteInventors: Sih-Han Li, Shih-Chieh Chang, Shyh-Shyuan Sheu, Jian-Wei Su, Fu-Cheng Tsai
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Publication number: 20190202623Abstract: An auxiliary clamping operation device detachably securable to a spray can is disclosed to include a grip. The grip includes two clamping parts disposed at one end thereof, and a receiving space defined between the two clamping parts. Each clamping part has a triggering portion and a positioning portion disposed on opposite sides. The two trigger portions are fastened together so that the two positioning portions are drivable by the trigger portions to move between an open position where the spray can is separable from the clamping parts, and a close position where the clamping parts clamp the spray can.Type: ApplicationFiled: December 28, 2018Publication date: July 4, 2019Inventor: Fu-Cheng TSAI