Abstract: A semiconductor die includes an array of first capacitor regions, each of the first capacitor regions including multiple first capacitor cell structures, wherein each first capacitor cell structure includes a plurality of first trench segments characterized by a first trench length, a first trench width, and a first trench spacing, and a first air gap width in a gap-filling material. The semiconductor die also includes a plurality of second capacitor regions interspersed in the array of first capacitor regions, each of the second capacitor region including multiple second capacitor cell structures, wherein each second capacitor cell structures includes a plurality of second trench segments characterized by a second trench length, a second trench width, a second trench spacing, and a second air gap width in the gap-filling material.

Abstract: A semiconductor arrangement and method of forming the semiconductor arrangement are provided. The semiconductor arrangement includes a first conductive layer and a first dielectric layer over the first conductive layer. A second conductive layer is over a portion of the first dielectric layer and has a sidewall surface. A spacer is over a portion of the sidewall surface of the second conductive layer and covers an interface between the second conductive layer and the first dielectric layer.

Abstract: A capacitance structure comprises a metal nitride layer, such as a titanium nitride (TiN) layer, a compositionally graded film formed on a surface of the metal nitride layer by thermal oxidation, and a dielectric layer disposed on the compositionally graded film. A method of manufacturing a capacitance structure includes forming a conductive layer, performing thermal oxidation of a surface of the conductive layer to produce a compositionally graded film on the conductive layer, and forming a dielectric layer on the compositionally graded film.

Abstract: A semiconductor device includes: at least one conductive feature disposed on a substrate; at least one dielectric layer overlying the substrate, a trench structure extending through the at least one dielectric layer; and a protection layer overlaying the trench structure.

Abstract: A semiconductor device includes: at least one conductive feature disposed on a substrate; at least one dielectric layer overlying the substrate, a trench structure extending through the at least one dielectric layer; and a protection layer overlaying the trench structure.

Abstract: A semiconductor device includes: at least one conductive feature disposed on a substrate; at least one dielectric layer overlying the substrate, a trench structure extending through the at least one dielectric layer; and a protection layer overlaying the trench structure.

Abstract: A semiconductor device includes: at least one conductive feature disposed on a substrate; at least one dielectric layer overlying the substrate, a trench structure extending through the at least one dielectric layer; and a protection layer overlaying the trench structure.

Abstract: A method of forming a trench structure is provided. The method includes depositing a silicon carbide (SiC) layer on a top metal layer, forming a first passivation layer on the SiC layer, removing a portion of the first passivation layer to form a first opening, forming a second passivation layer on the first passivation layer, the second passivation layer including a first portion in the first opening, and forming a second opening by removing a part of the first portion of the second passivation layer. The forming the second opening exposes the top metal layer.

Abstract: A method of forming a trench structure is provided. The method includes depositing a silicon carbide (SiC) layer on a top metal layer, forming a first passivation layer on the SiC layer, removing a portion of the first passivation layer to form a first opening, forming a second passivation layer on the first passivation layer, the second passivation layer including a first portion in the first opening, and forming a second opening by removing a part of the first portion of the second passivation layer. The forming the second opening exposes the top metal layer.

Abstract: A semiconductor device includes: at least one conductive feature disposed on a substrate; at least one dielectric layer overlying the substrate, a trench structure extending through the at least one dielectric layer; and a protection layer overlaying the trench structure.

Abstract: A trench structure includes a top metal layer, a silicon carbide (SiC) layer on the top metal layer, a first passivation layer overlying the SiC layer, and a second passivation layer overlying the first passivation layer. The trench structure also includes a first sidewall and a second sidewall that, together with the top metal layer, form a trench. At least one of the first sidewall or the second sidewall includes a sidewall of the second passivation layer and a sidewall of the SiC layer.

Abstract: A method of forming a deep trench in a semiconductor substrate includes: forming a first mask pattern over the semiconductor substrate, in which the first mask pattern has a first opening exposing a portion of the semiconductor substrate; forming a second mask pattern over the first mask pattern, in which the second mask pattern has a second opening substantially aligned with the first opening to expose the portion of the semiconductor substrate, and the second opening has a width greater than a width of the first opening to further expose a portion of the first mask pattern; and removing the portion of the semiconductor substrate, the portion of first mask pattern and another portion of the semiconductor substrate beneath the portion of the first mask pattern to form the deep trench.

Abstract: A method of forming a deep trench in a semiconductor substrate includes: forming a first mask pattern over the semiconductor substrate, in which the first mask pattern has a first opening exposing a portion of the semiconductor substrate; forming a second mask pattern over the first mask pattern, in which the second mask pattern has a second opening substantially aligned with the first opening to expose the portion of the semiconductor substrate, and the second opening has a width greater than a width of the first opening to further expose a portion of the first mask pattern; and removing the portion of the semiconductor substrate, the portion of first mask pattern and another portion of the semiconductor substrate beneath the portion of the first mask pattern to form the deep trench.