Abstract: A semiconductor chip and a manufacturing method thereof are provided. The semiconductor chip includes: an array of pillar structures, disposed on a front surface of the semiconductor chip, and respectively including a ground pillar and multiple working pillars laterally spaced apart from and substantially parallel with a line portion of the ground pillar; and dummy pillar structures, disposed on the front surface of the semiconductor chip and laterally surrounding the pillar structures. Active devices formed inside the semiconductor chip are electrically connected to the working pillar. The ground pillars of the pillar structures and the dummy pillar structures are electrically connected to form a current pathway on the front surface of the semiconductor chip.

Abstract: A leak-detecting shut-off device has a holding mount, a valve seat and an operating set. The holding mount has a connecting segment, a mounting segment, an expansion element and a pushing rod. The expansion element is mounted in the mounting segment. The pushing rod is mounted in the mounting segment, is mounted around the expansion element, and has a mounting cover and multiple pushing panels. The valve seat is connected to the holding mount and has a body, an inlet pipe and an outlet pipe. The body is mounted in the connecting segment and has two connecting boards. The operating set is connected to the valve seat and has a valve shaft, a spring and an operating tab. The valve shaft is movably mounted in the body. The operating tab is connected to the connecting boards, is selectively moved above the pushing rod and abuts against the valve shaft.

Abstract: A leak-detecting shut-off device has a holding mount, a valve seat and an operating set. The holding mount has a connecting segment, a mounting segment, an expansion element and a pushing rod. The expansion element is mounted in the mounting segment. The pushing rod is mounted in the mounting segment, is mounted around the expansion element, and has a mounting cover and multiple pushing panels. The valve seat is connected to the holding mount and has a body, an inlet pipe and an outlet pipe. The body is mounted in the connecting segment and has two connecting boards. The operating set is connected to the valve seat and has a valve shaft, a spring and an operating tab. The valve shaft is movably mounted in the body. The operating tab is connected to the connecting boards, is selectively moved above the pushing rod and abuts against the valve shaft.

Abstract: A module and apparatus for measuring temperature related properties of an SRAM IC includes circuitry for controlling writing of data to and reading of data from a pair of SRAM ICs, one of which is a control and the other of which is the SRAM IC being tested. The circuitry includes an address counter, a logic controller, two input buffers, two output data latches, and a data comparator, the effect of temperature on data input through the input buffers under control of the logic controller and address counter being analyzed by comparing data output through the data latches. In addition, the apparatus includes two separate seats for the respective SRAM ICs, one of which is subjected to a constantly controlled temperature and the other of which is subjected to a varying ambient temperature.

Abstract: A device for raising voltage comprises a first element for providing a first output pin with a voltage raise in response to a first voltage change at a first input pin, and for providing a second output pin with a voltage raise in response to a second voltage change at a second input pin; and a second element for driving, when the voltage at the first output pin becomes higher than the voltage at the second output pin due to the first voltage change at the first input pin, the second output pin to maintain a voltage keeping pace with the voltage at the first output pin, and for driving, when the voltage at the second output pin becomes higher than the voltage at the first output pin due to the second voltage change at the second input pin, the first output pin to maintain a voltage keeping pace with the voltage at the second output pin.

Abstract: An apparatus for page mode programming of an EEPROM cell array applications is described. The apparatus comprises a control gate potential control means and a bit line potential control means. The control gate potential control means is connected to the control gate of the EEPROM cell to select the potential for the control gate of the EEPROM cell, while the bit line potential control means is connected to the bit line of the EEPROM cell to select the potential for the bit line. A bit line of the EEPROM cell is first selected by a bit line control signal, then a control gate control signal determines whether provides the high voltage to the control gate of the EEPROM cell.