Abstract: A semiconductor package with a support structure and a fabrication method thereof are provided. With a chip being electrically connected to electrical contacts formed on a carrier, a molding process is performed. A plurality of recessed portions formed on the carrier are filled with an encapsulant for encapsulating the chip during the molding process. After the carrier is removed, the part of the encapsulant filling the recessed portions forms outwardly protruded portions on a surface of the encapsulant, such that the semiconductor package can be attached to an external device via the protruded portions.

Abstract: A semiconductor package with a support structure and a fabrication method thereof are provided. With a chip being electrically connected to electrical contacts formed on a carrier, a molding process is performed. A plurality of recessed portions formed on the carrier are filled with an encapsulant for encapsulating the chip during the molding process. After the carrier is removed, the part of the encapsulant filling the recessed portions forms outwardly protruded portions on a surface of the encapsulant, such that the semiconductor package can be attached to an external device via the protruded portions.

Abstract: A semiconductor package without a chip carrier includes an insulating structure having an opening; an electroplated die pad provided in the opening; a chip attached to the electroplated die pad by a thermally conductive adhesive; a plurality of electrical contacts formed around the electroplated die pad, wherein at least one of the electrical contacts is provided on a top surface of the insulating structure, and the chip is electrically connected to the electrical contacts; and an encapsulant for encapsulating the chip, the insulating structure and the electrical contacts, wherein bottom surfaces of the insulating structure, the electroplated die pad and the electrical contacts, except the at least one electrical contact provided on the top surface of the insulating structure, are exposed from the encapsulant and are flush with a bottom surface of the encapsulant. A fabrication method of the semiconductor package is also provided.

Abstract: A carrier-free semiconductor package and a fabrication method thereof are provided. The fabrication method includes the steps of: providing a carrier having a plurality of electrical contacts formed thereon; mounting at least one chip on the carrier; electrically connecting the chip to the electrical contacts via a plurality of bonding wires; forming a coating layer on each of the electrical contacts to encapsulate a bonded end of each of the bonding wires on the electrical contacts; performing a molding process to form an encapsulant for encapsulating the chip, the bonding wires and the electrical contacts; and removing the carrier, such that bottom surfaces of the electrical contacts are exposed from the encapsulant. This obtains a semiconductor package not having a carrier, and the coating layers can enhance adhesion between the electrical contacts and the encapsulant.

Abstract: A semiconductor package with a support structure and a fabrication method thereof are provided. With a chip being electrically connected to electrical contacts formed on a carrier, a molding process is performed. A plurality of recessed portions formed on the carrier are filled with an encapsulant for encapsulating the chip during the molding process. After the carrier is removed, the part of the encapsulant filling the recessed portions forms outwardly protruded portions on a surface of the encapsulant, such that the semiconductor package can be attached to an external device via the protruded portions.

Abstract: A method of manufacturing a quad flat non-leaded semiconductor package is provided. A metal plate is prepared and is defined with predetermined positions of a plurality of electrically conductive pads. A resist layer is formed on the metal plate, and a plurality of openings are formed in the resist layer and correspond to the predetermined positions of the electrically conductive pads. A solderable metal plated layer is formed in each of the openings of the resist layer. The resist layer on the metal plate is removed. A portion of the metal plate, which is not covered by the metal plated layers, is etched using the metal plated layers as a mask. A chip is mounted on the metal plate and is electrically connected to the electrically conductive pads. A molding process is performed such that the chip and the metal plate are encapsulated by an encapsulant.

Abstract: A carrier-free semiconductor package with a stand-off member and a fabrication method thereof are proposed. A carrier with a recessed portion and a plurality of electrical contacts on a surface of the carrier is provided. At least one chip is mounted to the recessed portion of the carrier and is electrically connected to the electrical contacts. An encapsulant is formed on the carrier, for encapsulating the recessed portion, the chip, and the electrical contacts. Finally, the carrier is removed such that the semiconductor package with the stand-off member protruded from a bottom surface thereof is formed. The stand-off member is used for maintaining a predetermined mounting distance between the semiconductor package and an external device, such that problems in the prior art such as reduced fatigue lifetime and cracks of solder joints due to concentration of thermal stress on the solder joints can be overcome in the present invention.

Abstract: A semiconductor package without a chip carrier includes an insulating structure having an opening; an electroplated die pad provided in the opening; a chip attached to the electroplated die pad by a thermally conductive adhesive; a plurality of electrical contacts formed around the electroplated die pad, wherein at least one of the electrical contacts is provided on a top surface of the insulating structure, and the chip is electrically connected to the electrical contacts; and an encapsulant for encapsulating the chip, the insulating structure and the electrical contacts, wherein bottom surfaces of the insulating structure, the electroplated die pad and the electrical contacts, except the at least one electrical contact provided on the top surface of the insulating structure, are exposed from the encapsulant and are flush with a bottom surface of the encapsulant. A fabrication method of the semiconductor package is also provided.

Abstract: A wire-bonding method and a semiconductor package using the same are provided. The semiconductor package includes a carrier; a chip mounted on the carrier; a plurality of first wires and second wires alternatively arranged in a stagger manner, with a wire loop of each second wire being downwardly bent to form a deformed portion so as to provide a height different between the wire loops of each first wire and each second wire, wherein the first and second wires electrically connect the chip to the carrier; and an encapsulant for encapsulating the chip, the first wires, the second wires and a portion of the carrier. The height difference between the wire loops of each first wire and each second wire increases a pitch between adjacent first and second wires thereby preventing the wires from contact and short circuit with each other due to wire sweep during an encapsulation process.

Abstract: A wire-bonding method and a semiconductor package using the same are provided. The semiconductor package includes a carrier; a chip mounted on the carrier; a plurality of first wires and second wires alternatively arranged in a stagger manner, with a wire loop of each second wire being downwardly bent to form a deformed portion so as to provide a height different between the wire loops of each first wire and each second wire, wherein the first and second wires electrically connect the chip to the carrier; and an encapsulant for encapsulating the chip, the first wires, the second wires and a portion of the carrier. The height difference between the wire loops of each first wire and each second wire increases a pitch between adjacent first and second wires thereby preventing the wires from contact and short circuit with each other due to wire sweep during an encapsulation process.

Abstract: A lead-frame-based semiconductor package and a lead frame thereof are proposed. The semiconductor package includes: the lead frame having at least one die pad and a plurality of leads around the die pad, wherein a plurality of grooves and runners are formed on a surface of the die pad, and each of the grooves is connected to an edge of the die pad by at least one of the runners; at least one chip mounted on the other surface of the die pad and electrically connected to the plurality of leads; and an encapsulant for encapsulating the chip, with the runners and grooves being exposed from the encapsulant. Thus, the flash problem in the prior art can be solved by means of the runners and grooves.

Abstract: A carrier-free semiconductor package and a fabrication method thereof are provided. The fabrication method includes the steps of: providing a carrier having a plurality of electrical contacts formed thereon; mounting at least one chip on the carrier; electrically connecting the chip to the electrical contacts via a plurality of bonding wires; forming a coating layer on each of the electrical contacts to encapsulate a bonded end of each of the bonding wires on the electrical contacts; performing a molding process to form an encapsulant for encapsulating the chip, the bonding wires and the electrical contacts; and removing the carrier, such that bottom surfaces of the electrical contacts are exposed from the encapsulant. This obtains a semiconductor package not having a carrier, and the coating layers can enhance adhesion between the electrical contacts and the encapsulant.

Abstract: A wire-bonding method and a semiconductor package using the same are provided. The semiconductor package includes a carrier; a chip mounted on the carrier; a plurality of first wires and second wires alternatively arranged in a stagger manner, with a wire loop of each second wire being downwardly bent to form a deformed portion so as to provide a height different between the wire loops of each first wire and each second wire, wherein the first and second wires electrically connect the chip to the carrier; and an encapsulant for encapsulating the chip, the first wires, the second wires and a portion of the carrier. The height difference between the wire loops of each first wire and each second wire increases a pitch between adjacent first and second wires thereby preventing the wires from contact and short circuit with each other due to wire sweep during an encapsulation process.

Abstract: An encapsulated semiconductor device includes a lead frame formed with a flash-proof body. The flash-proof body includes a dam bar formed on atop surface of the lead frame and a tape adhered to a bottom surface of the lead frame, where the dam bar is attached to both the lead frame and the tape. The semiconductor device further includes an encapsulation body having a core-hollowed portion integrated with the lead frame, the core-hollowed portion being bordered by the dam bar and the tape so that a semiconductor chip and conductive elements are exposed in the encapsulation body. A lid can be adhered to the encapsulation body to air-tightly seal the semiconductor chip and encapsulation elements in the core-hollowed portion.

Abstract: A semiconductor package with a heat dissipating structure is provided, including a lead frame with a die pad for allowing a chip to be mounted on an upper surface of the die pad, and a heat sink abutting against a lower surface of the die pad. A top surface of the heat sink, in contact with the lower surface of the die pad, is formed with at least a recessed portion. During a molding process of using a resin material to form an encapsulant for encapsulating the chip, lead frame and heat sink, the resin material fills into the recessed portion and forms a supporting member between the die pad and heat sink to provide support for a central portion of the die pad, so as to prevent the chip from cracking in a step of building up a packing pressure of the molding process, thereby assuring yield and reliability of fabricated products.

Abstract: A leadframe with a dot array of silver-plated regions on die pad is proposed, which is designed specifically for use in the construction of an exposed-pad type of semiconductor package. The proposed leadframe is characterized by that the front side of the die pad is partitioned into a centrally-located die-mounting area and a peripherally-located ground-wire bonding area; and wherein the die-mounting area is selectively silver-plated to form a dot array of silver-plated regions, while the peripheral area of the die pad is entirely silver-plated to form a silver-plated peripheral area. In addition, the die-mounting area of the die pad can be further formed with a plurality of dimples for the purpose of increasing the contact area between the die pad and a silver-epoxy layer that is to be pasted over the die-mounting area for use to adhere a semiconductor chip to the die pad.

Abstract: An encapsulated semiconductor packaging device having a flash-proof body comprises the following steps. A lead frame having a die pad and a plurality of leads is provided so that the inner portion of each lead frame is separated from the lateral side of the die pad is be formed as a gap there between. Then, the tape is attached to the bottom surfaces of the die pad and the lead frame so as to seal the bottom opening of gap. A dam bar is formed on inner ends of the leads so as to be tightly attached to each lead and a tape, Therefore, the inner ends of the leads and the dam bar are regarded as a wire bonding area. Furthermore, the dam bar is attached to the leads and the tape below each lead so that the dam bar and the tape is formed as a flash-proof structure. Therefore, after the lead frame is placed into the package mold for forming a package, the encapsulation body having a core-hollowed portion is formed.