Abstract: Apparatus and associated methods relate to a consolidated power-on-reset system (PORS) at a system-on-chip (SoC) level. In an illustrative example, an integrated circuit may include a first power domain and a second power region. A level shifter circuit may be coupled to translate data from the first power domain to the second power domain. A PORS including a voltage detection circuit, a glitch filter circuit, and logic gates may be configured to generate isolation signals between the first power domain and the second power domain. The level shifter circuit may be enabled in response to the generated isolation signals. By using the isolation signals, multiple power domains on IC may be managed comprehensively during power-up to avoid unstable operation.

Abstract: Leakage current estimation for a circuit can include generating a cell leakage library including cell-level leakage current geometry data for different states of cells of a cell library, wherein the cells are specified as transistor-level netlists, and determining, using a processor, gate-level leakage current geometry data for gates of a gate-level netlist for the circuit based upon states of the gates for a selected operating state of the circuit and the cell-level leakage current geometry data. Total leakage current geometry data can be determined, using the processor, for the gate-level netlist by aggregating the gate-level leakage current geometry data.

Abstract: Techniques for adaptively scaling power supply voltage of a programmable integrated circuit. Compact speed-testing ring oscillators are inserted into a pre-constructed circuit model to test the speed of speed-critical aspects of the interconnect fabric of the programmable integrated circuit. The speed-testing ring oscillators are compact due to including only two elements configured from lookup table elements (“LUTs”) of the programmable integrated circuit. The speed-testing ring oscillators are connected to a power management unit which receives speed values output from the speed-testing ring oscillators and adjusts the power supply voltage to maintain the speed-testing ring oscillators operating at or above a prescribed speed. If all speed-testing ring oscillators are operating too fast, then power management unit reduces voltage to reduce the total power consumed by the programmable integrated circuit while still maintaining operation above a desired speed.

Abstract: In an example implementation, a level-shifter circuit in an integrated circuit (IC) includes a plurality field-effect transistors (FETs) coupled to provide: a first inverter having an input port configured to receive an input signal having a first supply voltage, an output port, and a bias port; a second inverter having an input port coupled to the output port of the first inverter, an output port, and a bias port coupled to a second supply voltage; a diode-connected FET coupled between the second supply voltage and the bias port of the first inverter; a first FET in parallel with the diode-connected FET having a gate coupled to the output of the second inverter; and a second FET in parallel with the diode-connected FET and the first FET having a gate configured to receive a mode select signal.

Abstract: In an example implementation, a level-shifter circuit in an integrated circuit (IC) includes a plurality field-effect transistors (FETs) coupled to provide: a first inverter having an input port configured to receive an input signal having a first supply voltage, an output port, and a bias port; a second inverter having an input port coupled to the output port of the first inverter, an output port, and a bias port coupled to a second supply voltage; a diode-connected FET coupled between the second supply voltage and the bias port of the first inverter; a first FET in parallel with the diode-connected FET having a gate coupled to the output of the second inverter; and a second FET in parallel with the diode-connected FET and the first FET having a gate configured to receive a mode select signal.

Abstract: Approaches for generating delay values for instances of a circuit include inputting possible contexts of the circuit. Each context includes a respective delay value and a combination of possible types of a plurality of characteristics of the circuit, and each characteristic is of one type of a plurality of alternative types of the characteristic. A plurality of classification parameters is input and the classification parameters indicate selected ones of the characteristics. Groups of contexts are selected based on the plurality of classification parameters. Each group includes one or more of the contexts, and each context includes the plurality of characteristics. A combination of types of the selected characteristics in each context in a group is equal to the combination of types of the selected characteristics of each other context in the group. For each group, a mean and a standard deviation of the respective delay values are determined and output.

Abstract: An input/output (“I/O”) circuit has a first N-channel metal-oxide semiconductor (“NMOS”) field-effect transistor (“FET”) coupled to the input pin with a silicide block. A first P-channel metal-oxide semiconductor (“PMOS”) FET is directly connected to the input pin, with its N-well electrically coupled to an ESD well bias circuit. An NMOS low-voltage differential signal (“LVDS”) driver is also directly connected to the input pin, and has cascaded NMOS FETs. The first NMOS FET of the LVDS driver is fabricated within a first P-tap guard ring electrically coupled to ground and an N-well guard ring coupled to the ESD well bias. The second NMOS FET of the LVDS driver is fabricated within a second P-tap guard ring electrically coupled to ground.

Abstract: An input/output (“I/O”) circuit has a first N-channel metal-oxide semiconductor (“NMOS”) field-effect transistor (“FET”) coupled to the input pin with a silicide block. A first P-channel metal-oxide semiconductor (“PMOS”) FET is directly connected to the input pin, with its N-well electrically coupled to an ESD well bias circuit. An NMOS low-voltage differential signal (“LVDS”) driver is also directly connected to the input pin, and has cascaded NMOS FETs. The first NMOS FET of the LVDS driver is fabricated within a first P-tap guard ring electrically coupled to ground and an N-well guard ring coupled to the ESD well bias. The second NMOS FET of the LVDS driver is fabricated within a second P-tap guard ring electrically coupled to ground.

Abstract: An Electrostatic Discharge (ESD) protection device extends the protection range of an ESD clamp circuit through hysteresis of the associated ESD clamp control circuit. Once the ESD clamp circuit is activated, an adjustment circuit applies a trigger level adjustment signal to the ESD clamp control circuit. The trigger level adjustment signal effectively increases the magnitude of the deactivation signal that is required to deactivate the ESD clamp circuit. Since the deactivation signal increases over time, a longer activation time of the ESD protection device is provided, which allows an extended protection range.

Abstract: An Electrostatic Discharge (ESD) protection circuit activates an ESD conduction circuit in response to an ESD event. A deactivation circuit generates an exponentially increasing deactivation signal in response to the ESD event, such that once the deactivation signal has increased to a trigger point of a control circuit, the ESD conduction circuit is deactivated. An active resistance component within the deactivation circuit incorporates a biasing element to maintain a resistance value of the active resistance component substantially constant over all operating conditions.