Patents by Inventor Fu-Hsien Wang
Fu-Hsien Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240120295Abstract: A semiconductor chip and a manufacturing method thereof are provided. The semiconductor chip includes: an array of pillar structures, disposed on a front surface of the semiconductor chip, and respectively including a ground pillar and multiple working pillars laterally spaced apart from and substantially parallel with a line portion of the ground pillar; and dummy pillar structures, disposed on the front surface of the semiconductor chip and laterally surrounding the pillar structures. Active devices formed inside the semiconductor chip are electrically connected to the working pillar. The ground pillars of the pillar structures and the dummy pillar structures are electrically connected to form a current pathway on the front surface of the semiconductor chip.Type: ApplicationFiled: January 30, 2023Publication date: April 11, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Szu-Hsien Lee, Yun-Chung Wu, Pei-Wei Lee, Fu Wei Liu, Jhao-Yi Wang
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Patent number: 8802469Abstract: A method for the separation of multiple dies during semiconductor fabrication is described. On an upper surface of a semiconductor wafer containing multiple dies, metal layers are deposited everywhere except where a block of stop electroplating material exists. The stop electroplating material is obliterated, and a barrier layer is formed above the entire remaining structure. A sacrificial metal element is added above the barrier layer, and then the substrate is removed. After the semiconductor material between the individual dies is eradicated, any desired bonding pads and patterned circuitry are added to the semiconductor surface opposite the sacrificial metal element, a passivation layer is added to this surface, and then the sacrificial metal element is removed. Tape is added to the now exposed barrier layer, the passivation layer is removed, the resulting structure is flipped over, and the tape is expanded to separate the individual dies.Type: GrantFiled: May 17, 2011Date of Patent: August 12, 2014Assignee: SemiLEDS Optoelectronics Co., Ltd.Inventors: Chen-Fu Chu, Trung Tri Doan, Hao-Chun Cheng, Feng-Hsu Fan, Fu-Hsien Wang
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Patent number: 8716041Abstract: A method for fabricating a light emitting diode includes the steps of providing a thermal conductive substrate having an electrical isolation layer, forming an anode via and a cathode via side by side on a first side of the substrate part way through the substrate, forming an anode through interconnect in the anode via and a cathode through interconnect in the cathode via, thinning the substrate from a second side of the substrate to the anode through interconnect and the cathode through interconnect, and mounting a LED chip to the first side in electrical communication with the cathode through interconnect and the anode through interconnect.Type: GrantFiled: August 22, 2013Date of Patent: May 6, 2014Assignee: SemiLEDS Optoelectrics Co., Ltd.Inventors: Trung Tri Doan, Chen-Fu Chu, Wen-Huang Liu, Feng-Hsu Fan, Hao-Chun Cheng, Fu-Hsien Wang
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Publication number: 20130337590Abstract: A method for fabricating a light emitting diode includes the steps of providing a thermal conductive substrate having an electrical isolation layer, forming an anode via and a cathode via side by side on a first side of the substrate part way through the substrate, forming an anode through interconnect in the anode via and a cathode through interconnect in the cathode via, thinning the substrate from a second side of the substrate to the anode through interconnect and the cathode through interconnect, and mounting a LED chip to the first side in electrical communication with the cathode through interconnect and the anode through interconnect.Type: ApplicationFiled: August 22, 2013Publication date: December 19, 2013Applicant: SemiLEDS Optoelectronics Co., Ltd.Inventors: TRUNG TRI DOAN, Chen-Fu Chu, Wen-Huang Liu, Feng-Hsu Fan, Hao-Chun Cheng, Fu-Hsien Wang
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Patent number: 8552458Abstract: A light emitting diode includes a thermal conductive substrate having at least one electrical isolation layer configured to provide vertical electrical isolation and a heat transfer path through the substrate from a front side (first side) to a back side (second side) thereof. The light emitting diode includes an anode having a through interconnect, and a cathode having a through interconnect, which are arranged side by side on the substrate. The light emitting diode also includes a LED chip mounted to the substrate between the anode and the cathode.Type: GrantFiled: June 26, 2010Date of Patent: October 8, 2013Assignee: SemiLEDS Optoelectronics Co., Ltd.Inventors: Trung Tri Doan, Chen-Fu Chu, Wen-Huang Liu, Feng-Hsu Fan, Hao-Chun Cheng, Fu-Hsien Wang
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Publication number: 20110316034Abstract: A light emitting diode includes a thermal conductive substrate having at least one electrical isolation layer configured to provide vertical electrical isolation and a heat transfer path through the substrate from a front side (first side) to a back side (second side) thereof. The light emitting diode includes an anode having a through interconnect, and a cathode having a through interconnect, which are arranged side by side on the substrate. The light emitting diode also includes a LED chip mounted to the substrate between the anode and the cathode.Type: ApplicationFiled: June 26, 2010Publication date: December 29, 2011Inventors: Trung Tri Doan, Chen-Fu Chu, Wen-Huang Liu, Feng-Hsu Fan, Hao-Chun Cheng, Fu-Hsien Wang
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Publication number: 20110217799Abstract: A method for the separation of multiple dies during semiconductor fabrication is described. On an upper surface of a semiconductor wafer containing multiple dies, metal layers are deposited everywhere except where a block of stop electroplating material exists. The stop electroplating material is obliterated, and a barrier layer is formed above the entire remaining structure. A sacrificial metal element is added above the barrier layer, and then the substrate is removed. After the semiconductor material between the individual dies is eradicated, any desired bonding pads and patterned circuitry are added to the semiconductor surface opposite the sacrificial metal element, a passivation layer is added to this surface, and then the sacrificial metal element is removed. Tape is added to the now exposed barrier layer, the passivation layer is removed, the resulting structure is flipped over, and the tape is expanded to separate the individual dies.Type: ApplicationFiled: May 17, 2011Publication date: September 8, 2011Inventors: Chen-Fu Chu, Trung Tri Doan, Hao-Chun Cheng, Feng-Hsu Fan, Fu-Hsien Wang
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Patent number: 7968379Abstract: A method for the separation of multiple dies during semiconductor fabrication is described. On an upper surface of a semiconductor wafer containing multiple dies, metal layers are deposited everywhere except where a block of stop electroplating material exists. The stop electroplating material is obliterated, and a barrier layer is formed above the entire remaining structure. A sacrificial metal element is added above the barrier layer, and then the substrate is removed. After the semiconductor material between the individual dies is eradicated, any desired bonding pads and patterned circuitry are added to the semiconductor surface opposite the sacrificial metal element, a passivation layer is added to this surface, and then the sacrificial metal element is removed. Tape is added to the now exposed barrier layer, the passivation layer is removed, the resulting structure is flipped over, and the tape is expanded to separate the individual dies.Type: GrantFiled: November 18, 2008Date of Patent: June 28, 2011Assignee: SemiLEDs Optoelectronics Co., Ltd.Inventors: Chen-Fu Chu, Trung Tri Doan, Hao-Chun Cheng, Feng-Hsu Fan, Fu-Hsien Wang
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Publication number: 20090093075Abstract: A method for the separation of multiple dies during semiconductor fabrication is described. On an upper surface of a semiconductor wafer containing multiple dies, metal layers are deposited everywhere except where a block of stop electroplating material exists. The stop electroplating material is obliterated, and a barrier layer is formed above the entire remaining structure. A sacrificial metal element is added above the barrier layer, and then the substrate is removed. After the semiconductor material between the individual dies is eradicated, any desired bonding pads and patterned circuitry are added to the semiconductor surface opposite the sacrificial metal element, a passivation layer is added to this surface, and then the sacrificial metal element is removed. Tape is added to the now exposed barrier layer, the passivation layer is removed, the resulting structure is flipped over, and the tape is expanded to separate the individual dies.Type: ApplicationFiled: November 18, 2008Publication date: April 9, 2009Inventors: Chen-Fu Chu, Trung Tri Doan, Hao-Chun Cheng, Feng-Hsu Fan, Fu-Hsien Wang
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Patent number: 7452739Abstract: A method for the separation of multiple dies during semiconductor fabrication is described. On an upper surface of a semiconductor wafer containing multiple dies, metal layers are deposited everywhere except where a block of stop electroplating material exists. The stop electroplating material is obliterated, and a barrier layer is formed above the entire remaining structure. A sacrificial metal element is added above the barrier layer, and then the substrate is removed. After the semiconductor material between the individual dies is eradicated, any desired bonding pads and patterned circuitry are added to the semiconductor surface opposite the sacrificial metal element, a passivation layer is added to this surface, and then the sacrificial metal element is removed. Tape is added to the now exposed barrier layer, the passivation layer is removed, the resulting structure is flipped over, and the tape is expanded to separate the individual dies.Type: GrantFiled: March 6, 2007Date of Patent: November 18, 2008Assignee: Semi-Photonics Co., Ltd.Inventors: Chen-Fu Chu, Trung Tri Doan, Hao-Chun Cheng, Feng-Hsu Fan, Fu-Hsien Wang
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Publication number: 20070212854Abstract: A method for the separation of multiple dies during semiconductor fabrication is described. On an upper surface of a semiconductor wafer containing multiple dies, metal layers are deposited everywhere except where a block of stop electroplating material exists. The stop electroplating material is obliterated, and a barrier layer is formed above the entire remaining structure. A sacrificial metal element is added above the barrier layer, and then the substrate is removed. After the semiconductor material between the individual dies is eradicated, any desired bonding pads and patterned circuitry are added to the semiconductor surface opposite the sacrificial metal element, a passivation layer is added to this surface, and then the sacrificial metal element is removed. Tape is added to the now exposed barrier layer, the passivation layer is removed, the resulting structure is flipped over, and the tape is expanded to separate the individual dies.Type: ApplicationFiled: March 6, 2007Publication date: September 13, 2007Inventors: Chen-Fu Chu, Trung Tri Doan, Hao-Chun Cheng, Feng-Hsu Fan, Fu-Hsien Wang