Patents by Inventor Fu-Hsing Chen

Fu-Hsing Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11035724
    Abstract: An optical sensing circuit includes a first light sensor, a second light sensor, a third light sensor, a capacitor, and a sampling circuit. The first light sensor, the second light sensor, and the third light sensor are respectively covered by a first color filter, a second color filter, and a third color filter. The first light sensor is coupled to the capacitor, the sampling circuit, and the third light sensor. The second light sensor is coupled to the first light sensor and is configured to receive a first sensing signal. The third light sensor is coupled between the first light sensor and a voltage source.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: June 15, 2021
    Assignees: AU OPTRONICS CORPORATION, NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Chih-Lung Lin, Fu-Hsing Chen, Chia-Lun Lee, Chia-En Wu, Jian-Shen Yu
  • Publication number: 20200158567
    Abstract: An optical sensing circuit includes a first light sensor, a second light sensor, a third light sensor, a capacitor, and a sampling circuit. The first light sensor, the second light sensor, and the third light sensor are respectively covered by a first color filter, a second color filter, and a third color filter. The first light sensor is coupled to the capacitor, the sampling circuit, and the third light sensor. The second light sensor is coupled to the first light sensor and is configured to receive a first sensing signal. The third light sensor is coupled between the first light sensor and a voltage source.
    Type: Application
    Filed: October 2, 2019
    Publication date: May 21, 2020
    Inventors: Chih-Lung LIN, Fu-Hsing CHEN, Chia-Lun LEE, Chia-En WU, Jian-Shen YU
  • Patent number: 10175098
    Abstract: An optical sensing circuit has a plurality of optical sensing units arranged so that the optical sensing circuit is ambient light insensitive or sensitive to light within certain spectrum. The sensitive spectra corresponding to the plurality of optical sensing units are different from one another.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: January 8, 2019
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Chih-Lung Lin, Chia-En Wu, Po-Syun Chen, Fu-Hsing Chen, Ming-Xun Wang, Ching-En Lee, Po-Cheng Lai, Jian-Shen Yu
  • Patent number: 9990893
    Abstract: A pixel circuit includes a first capacitor whose two terminals are coupled to a first node and a ground end respectively, a first switch whose two terminals are coupled to a second node and a fourth node respectively, a liquid crystal, a second switch, a pull-up circuit, a pull-down circuit, a second capacitor and a third switch. The first switch is coupled to the first node and a first data input end. The liquid crystal is coupled to the second and a third node. The second switch is coupled to the second node and a second data input end. The pull-up circuit is coupled to the first node and the second node and a node of a high voltage. The pull-down circuit is coupled to the second node, the fourth node and the ground end. The third switch is coupled to the fourth node and the ground end.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: June 5, 2018
    Assignee: AU OPTRONICS CORP.
    Inventors: Chih-Lung Lin, Jian-Shen Yu, Fu-Hsing Chen, Chia-Che Hung, Ze-yu Yen
  • Publication number: 20170276541
    Abstract: An optical sensing circuit has a plurality of optical sensing units arranged so that the optical sensing circuit is ambient light insensitive or sensitive to light within certain spectrum. The sensitive spectra corresponding to the plurality of optical sensing units are different from one another.
    Type: Application
    Filed: March 6, 2017
    Publication date: September 28, 2017
    Inventors: Chih-Lung LIN, Chia-En WU, Po-Syun CHEN, Fu-Hsing CHEN, Ming-Xun WANG, Ching-En LEE, Po-Cheng LAI, Jian-Shen YU
  • Publication number: 20170053611
    Abstract: A pixel circuit includes a first capacitor whose two terminals are coupled to a first node and a ground end respectively, a first switch whose two terminals are coupled to a second node and a fourth node respectively, a liquid crystal, a second switch, a pull-up circuit, a pull-down circuit, a second capacitor and a third switch. The first switch is coupled to the first node and a first data input end. The liquid crystal is coupled to the second and a third node. The second switch is coupled to the second node and a second data input end. The pull-up circuit is coupled to the first node and the second node and a node of a high voltage. The pull-down circuit is coupled to the second node, the fourth node and the ground end. The third switch is coupled to the fourth node and the ground end.
    Type: Application
    Filed: February 1, 2016
    Publication date: February 23, 2017
    Inventors: Chih-Lung LIN, Jian-Shen YU, Fu-Hsing CHEN, Chia-Che HUNG, Ze-yu YEN
  • Patent number: 9454942
    Abstract: A display panel includes gate lines and a gate driver. The gate driver includes series coupled driving stages, in which an N-th driving stage of the series-coupled driving stages includes a driving unit and an input control unit. The driving unit transmits a first clock signal according to a control voltage level of a control node, so as to output a gate-driving signal. The input control unit transmits the gate-driving signal outputted from an (N?1)-th driving stage to the control nodes, so as to adjust the control voltage level to one of a first voltage level and a second voltage level. A predetermined time interval is present between a rising edge of the first clock signal and a falling edge of the second clock signal. During the predetermined time interval, the control voltage level is pulled to the first voltage level by the input control unit.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: September 27, 2016
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Chih-Lung Lin, Yuan-Wei Du, Fu-Hsing Chen, Chun-Da Tu
  • Publication number: 20160118009
    Abstract: A display panel includes gate lines and a gate driver. The gate driver includes series coupled driving stages, in which an N-th driving stage of the series-coupled driving stages includes a driving unit and an input control unit. The driving unit transmits a first clock signal according to a control voltage level of a control node, so as to output a gate-driving signal. The input control unit transmits the gate-driving signal outputted from an (N?1)-th driving stage to the control nodes, so as to adjust the control voltage level to one of a first voltage level and a second voltage level. A predetermined time interval is present between a rising edge of the first clock signal and a falling edge of the second clock signal. During the predetermined time interval, the control voltage level is pulled to the first voltage level by the input control unit.
    Type: Application
    Filed: March 11, 2015
    Publication date: April 28, 2016
    Inventors: Chih-Lung LIN, Yuan-Wei DU, Fu-Hsing CHEN, Chun-Da TU
  • Patent number: 7668976
    Abstract: A computer system comprising a memory module, a connection port, and a central processing unit (CPU) is disclosed. The memory module stores a main base input/output system (BIOS) comprising an auxiliary function. The connection port is capable of connecting an auxiliary module comprising at least one specific program. The CPU executes the main BIOS when the auxiliary function is de-activated. The CPU executes the specific program when the auxiliary function is activated.
    Type: Grant
    Filed: August 13, 2007
    Date of Patent: February 23, 2010
    Assignee: Giga-Byte Technology Co., Ltd.
    Inventors: Chih-Jen Hou, Hsin-Teng Fu, Fu-Hsing Chen, Tai-Li Lin
  • Publication number: 20080301331
    Abstract: A computer system comprising a memory module, a connection port, and a central processing unit (CPU) is disclosed. The memory module stores a main base input/output system (BIOS) comprising an auxiliary function. The connection port is capable of connecting an auxiliary module comprising at least one specific program. The CPU executes the main BIOS when the auxiliary function is de-activated. The CPU executes the specific program when the auxiliary function is activated.
    Type: Application
    Filed: August 13, 2007
    Publication date: December 4, 2008
    Inventors: Chih-Jen Hou, Hsin-Teng Fu, Fu-Hsing Chen, Tai-Li Lin, Hao-Chien Hung