Abstract: Various 3D memory cells, array architectures, and processes are disclosed. In an embodiment, a memory cell structure is provided that is formed by a process of alternately depositing multiple semiconductor layers and sacrificial layers to form a stack, forming vertical bit line holes through the stack using a deep trench process, forming floating bodies in the semiconductor layers using an isotropic doping process through the bit line holes, depositing conductor material to fill the bit line holes, removing the sacrificial layers, depositing a gate dielectric layer between the semiconductor layers, and depositing gate material onto the gate dielectric layer.

Abstract: An improved method of catalytic gaseous chemical synthesis of pyridine by reaction of ammonia and a carbonyl compound, preferably with added hydrogen, is described herein. The process employs as the catalyst a crystalline aluminosilicate zeolite which has been ion exchanged with a Group VIII metal of the Periodic Table. The preferred metal is palladium. Suitably, the Group VIII metal is present in an amount of about 0.01% to 5% by weight of the catalyst, preferably 0.1% to 2%. The crystalline aluminosilicate zeolite catalyst suitably has a silica to alumina mole rate of at least 15, preferably 30 to 200, and optimally, about 120 to 150. The process of the invention provides a high and selective yield of pyridine over a prolonged reaction period, and affords facile restorability of the catalyst.