Patents by Inventor Fu-Kai Yang

Fu-Kai Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12057488
    Abstract: A semiconductor structure includes a fin protruding from a substrate, a first and a second metal gate stacks disposed over the fin, and a dielectric feature defining a sidewall of each of the first and the second metal gate stacks. Furthermore, the dielectric feature includes a two-layer structure, where sidewalls of the first layer are defined by the second layer, and where the first and the second layers have different compositions.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: August 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Han Chen, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Patent number: 12051628
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate, at least two gate structures disposed over the substrate, each of the at least two gate structures including a gate electrode and a spacer disposed along sidewalls of the gate electrode, wherein the spacer includes a refill portion and a bottom portion, the refill portion of the spacer has a funnel shape such that a top surface of the refill portion of the spacer is larger than a bottom surface of the refill portion of the spacer, and a source/drain contact disposed over the substrate and between the spacers of the at least two gate structures.
    Type: Grant
    Filed: October 31, 2022
    Date of Patent: July 30, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yu Yang, Yen-Ting Chen, Wei-Yang Lee, Fu-Kai Yang, Yen-Ming Chen
  • Patent number: 12051735
    Abstract: A method includes forming a first and a second dummy gate stack crossing over a semiconductor region, forming an ILD to embed the first and the second dummy gate stacks therein, replacing the first and the second dummy gate stacks with a first and a second replacement gate stack, respectively, performing a first etching process to form a first opening. A portion of the first replacement gate stack and a portion of the second replacement gate stack are removed. The method further includes filling the first opening to form a dielectric isolation region, performing a second etching process to form a second opening, with the ILD being etched, and the dielectric isolation region being exposed to the second opening, forming a contact spacer in the second opening, and filling a contact plug in the second opening. The contact plug is between opposite portions of the contact spacer.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: July 30, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ting-Gang Chen, Tai-Chun Huang, Ming-Chang Wen, Shu-Yuan Ku, Fu-Kai Yang, Tze-Liang Lee, Yung-Cheng Lu, Yi-Ting Fu
  • Publication number: 20240222433
    Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes nanostructures spaced apart from each other in a first direction and a gate structure formed over and around the nanostructures. The semiconductor structure further includes a gate spacer covering a sidewall of the gate structure and a source/drain structure attached to the nanostructures in a second direction. The semiconductor structure further includes a contact spaced apart from the gate structure by the gate spacer in the second direction and a first conductive structure landing over the gate structure. The semiconductor structure further includes a second conductive structure formed over the gate spacer. In addition, a portion of the second conductive structure is sandwiched between the first conductive structure and the contact.
    Type: Application
    Filed: March 14, 2024
    Publication date: July 4, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jia-Heng WANG, Pang-Chi WU, Chao-Hsun WANG, Fu-Kai YANG, Mei-Yun WANG
  • Publication number: 20240204069
    Abstract: In an embodiment, a device includes: a gate electrode; a epitaxial source/drain region adjacent the gate electrode; one or more inter-layer dielectric (ILD) layers over the epitaxial source/drain region; a first source/drain contact extending through the ILD layers, the first source/drain contact connected to the epitaxial source/drain region; a contact spacer surrounding the first source/drain contact; and a void disposed between the contact spacer and the ILD layers.
    Type: Application
    Filed: January 2, 2024
    Publication date: June 20, 2024
    Inventors: Chun-Han Chen, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Patent number: 12009363
    Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiments, a semiconductor device includes an n-type transistor region and a p-type transistor region. The n-type transistor region includes a first gate stack, a first gate spacer over sidewalls of the first gate stack, an n-type epitaxial feature in a source/drain (S/D) region of the n-type transistor region, and a first metal silicide layer over the n-type epitaxial feature. The p-type transistor region includes a second gate stack, a second gate spacer over sidewalls of the second gate stack, a p-type epitaxial feature in an S/D region of the p-type transistor region, a dopant-containing implant layer over the p-type epitaxial feature, and a second metal silicide layer over the dopant-containing implant layer. The dopant-containing implant layer includes a metallic dopant.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: June 11, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shao-Ming Koh, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Patent number: 12002863
    Abstract: A method includes forming a gate structure on a substrate, forming a seal spacer covering a sidewall of the gate structure, forming a sacrificial spacer covering a sidewall of the seal spacer, forming source/drain regions sandwiching a channel region that is under the gate structure, and depositing a contact etch stop layer covering a sidewall of the sacrificial spacer. The method further includes removing the sacrificial spacer to form a trench, wherein the trench exposes a sidewall of the contact etch stop layer and the sidewall of the seal spacer, and depositing an inter-layer dielectric layer, wherein the inter-layer dielectric layer caps the trench, thereby defining an air gap inside the trench.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: June 4, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kai-Hsuan Lee, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Yen-Ming Chen
  • Publication number: 20240174367
    Abstract: The present application provides a system for unmanned aerial vehicle (UAV) parachute landing. An exemplary system includes a detector configured to detect at least one of a flight speed, a wind speed, a wind direction, a position, a height, and a voltage of a UAV. The system also includes a memory storing instructions and a processor configured to execute the instructions to cause the system to: determine whether to open a parachute of the UAV in accordance with a criterion, responsive to the determination to open the parachute of the UAV, stop a motor of the UAV that spins a propeller of the UAV, and open the parachute of the UAV after stopping the motor of the UAV for a first period.
    Type: Application
    Filed: December 22, 2023
    Publication date: May 30, 2024
    Applicant: GEOSAT Aerospace & Technology
    Inventors: Lung-Shun SHIH, Fu-Kai YANG, Yi-Feng CHENG, Di-Yang WANG, Chien-Hsun LIAO
  • Patent number: 11990378
    Abstract: An embodiment method includes: forming fins extending from a semiconductor substrate; depositing an inter-layer dielectric (ILD) layer on the fins; forming masking layers on the ILD layer; forming a cut mask on the masking layers, the cut mask including a first dielectric material, the cut mask having first openings exposing the masking layers, each of the first openings surrounded on all sides by the first dielectric material; forming a line mask on the cut mask and in the first openings, the line mask having slot openings, the slot openings exposing portions of the cut mask and portions of the masking layers, the slot openings being strips extending perpendicular to the fins; patterning the masking layers by etching the portions of the masking layers exposed by the first openings and the slot openings; and etching contact openings in the ILD layer using the patterned masking layers as an etching mask.
    Type: Grant
    Filed: March 24, 2023
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Yuan Chen, Jui-Ping Lin, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Patent number: 11978664
    Abstract: A method includes forming a first conductive feature over a semiconductor substrate, forming an ILD layer over the first conductive feature, patterning the ILD layer to form a trench, and forming a conductive layer over the patterned ILD layer to fill the trench. The method further includes polishing the conductive layer to form a via contact configured to interconnect the first conductive feature with a second conductive feature, where polishing the conductive layer exposes a top surface of the ILD layer, polishing the exposed top surface of the ILD layer, such that a top portion of the via contact protrudes from the exposed top surface of the ILD layer, and forming the second conductive feature over the via contact, such that the top portion of the via contact extends into the second conductive feature.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pang-Sheng Chang, Chao-Hsun Wang, Kuo-Yi Chao, Fu-Kai Yang, Mei-Yun Wang, Li-Chieh Wu, Chun-Wei Hsu
  • Patent number: 11968817
    Abstract: A semiconductor device includes a fin structure. A source/drain region is formed on the fin structure. A first gate structure is disposed over the fin structure. A source/drain contact is disposed over the source/drain region. The source/drain contact has a protruding segment that protrudes at least partially over the first gate structure. The source/drain contact electrically couples together the source/drain region and the first gate structure.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: April 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jui-Lin Chen, Chao-Yuan Chang, Ping-Wei Wang, Fu-Kai Yang, Ting Fang, I-Wen Wu, Shih-Hao Lin
  • Patent number: 11961886
    Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate and nanostructures suspended over the substrate. The semiconductor structure also includes a gate structure wrapping around the nanostructures and a source/drain structure attached to the nanostructures. The semiconductor structure also includes a contact vertically over the source/drain structure and a first conductive structure vertically over the gate structure. The semiconductor structure also includes a second conductive structure in contact with a top surface of the first conductive structure and a top surface of the contact and including an extending portion laterally sandwiched between the first conductive structure and the contact.
    Type: Grant
    Filed: November 1, 2022
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jia-Heng Wang, Pang-Chi Wu, Chao-Hsun Wang, Fu-Kai Yang, Mei-Yun Wang
  • Publication number: 20240097035
    Abstract: Epitaxial source/drain structures for enhancing performance of multigate devices, such as fin-like field-effect transistors (FETs) or gate-all-around (GAA) FETs, and methods of fabricating the epitaxial source/drain structures, are disclosed herein. An exemplary device includes a dielectric substrate. The device further includes a channel layer, a gate disposed over the channel layer, and an epitaxial source/drain structure disposed adjacent to the channel layer. The channel layer, the gate, and the epitaxial source/drain structure are disposed over the dielectric substrate. The epitaxial source/drain structure includes an inner portion having a first dopant concentration and an outer portion having a second dopant concentration that is less than the first dopant concentration. The inner portion physically contacts the dielectric substrate, and the outer portion is disposed between the inner portion and the channel layer. In some embodiments, the outer portion physically contacts the dielectric substrate.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Inventors: Chen-Ming Lee, I-Wen Wu, Po-Yu Huang, Fu-Kai Yang, Mei-Yun Wang
  • Publication number: 20240096985
    Abstract: Methods and devices including an air gap adjacent a contact element extending to a source/drain feature of a device are described. Some embodiments of the method include depositing a dummy layer, which is subsequently removed to form the air gap. The dummy layer and subsequent air gap may be formed after a SAC dielectric layer such as silicon nitride is formed over an adjacent metal gate structure.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 21, 2024
    Inventors: I-Wen WU, Chen-Ming LEE, Fu-Kai YANG, Mei-Yun WANG
  • Publication number: 20240096999
    Abstract: A device includes a gate stack; a gate spacer on a sidewall of the gate stack; a source/drain region adjacent the gate stack; a silicide; and a source/drain contact electrically connected to the source/drain region through the silicide. The silicide includes a conformal first portion in the source/drain region, the conformal first portion comprising a metal and silicon; and a conformal second portion over the conformal first portion, the conformal second portion further disposed on a sidewall of the gate spacer, the conformal second portion comprising the metal, silicon, and nitrogen.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 21, 2024
    Inventors: Kai-Di Tzeng, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Patent number: 11935932
    Abstract: In an embodiment, a device includes: a gate electrode; a epitaxial source/drain region adjacent the gate electrode; one or more inter-layer dielectric (ILD) layers over the epitaxial source/drain region; a first source/drain contact extending through the ILD layers, the first source/drain contact connected to the epitaxial source/drain region; a contact spacer surrounding the first source/drain contact; and a void disposed between the contact spacer and the ILD layers.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: March 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Han Chen, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Publication number: 20240038593
    Abstract: A method includes forming first and second fins disposed on a substrate, forming a gate structure over the first and second fins, epitaxially growing a first source/drain (S/D) feature on the first fin and a second S/D feature on the second fin, depositing a dielectric layer covering the first and second S/D features, etching the dielectric layer to form a trench exposing the first and second S/D features, forming a metal structure in the trench and extending from the first S/D feature to the second S/D feature, performing a cut metal process to form an opening dividing the metal structure into a first segment over the first S/D feature and a second segment over the second S/D feature, and depositing an isolation feature in the opening. The isolation feature separates the first segment from the second segment.
    Type: Application
    Filed: June 13, 2023
    Publication date: February 1, 2024
    Inventors: Chung-Hao Cai, Chia-Hsien Yao, Yen-Jun Huang, Fu-Kai Yang, Mei-Yun Wang
  • Publication number: 20240038855
    Abstract: A method of forming a semiconductor structure includes providing a semiconductor substrate having a source/drain feature and a gate structure formed thereon; forming an interlayer dielectric layer on the semiconductor substrate; patterning the interlayer dielectric layer to form a trench to expose the source/drain feature within the trench; forming a dielectric liner on sidewalls of the trench; filling a metal layer in the trench; recessing a portion of the metal layer in the trench, thereby forming a recess in the metal layer; and refilling a dielectric material layer in the recess.
    Type: Application
    Filed: April 11, 2023
    Publication date: February 1, 2024
    Inventors: Chung-Hao CAI, Chao-Hsun WANG, Chia-Hsien YAO, Wang-Jung HSUEH, Yen-Jun HUANG, Fu-Kai YANG, Mei-Yun WANG
  • Patent number: 11884406
    Abstract: The present application provides a system for unmanned aerial vehicle (UAV) parachute landing. An exemplary system includes a detector configured to detect at least one of a flight speed, a wind speed, a wind direction, a position, a height, and a voltage of a UAV. The system also includes a memory storing instructions and a processor configured to execute the instructions to cause the system to: determine whether to open a parachute of the UAV in accordance with a criterion, responsive to the determination to open the parachute of the UAV, stop a motor of the UAV that spins a propeller of the UAV, and open the parachute of the UAV after stopping the motor of the UAV for a first period.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: January 30, 2024
    Assignee: GEOSAT Aerospace & Technology
    Inventors: Lung-Shun Shih, Fu-Kai Yang, Yi-Feng Cheng, Di-Yang Wang, Chien-Hsun Liao
  • Patent number: 11876135
    Abstract: Epitaxial source/drain structures for enhancing performance of multigate devices, such as fin-like field-effect transistors (FETs) or gate-all-around (GAA) FETs, and methods of fabricating the epitaxial source/drain structures, are disclosed herein. An exemplary device includes a dielectric substrate. The device further includes a channel layer, a gate disposed over the channel layer, and an epitaxial source/drain structure disposed adjacent to the channel layer. The channel layer, the gate, and the epitaxial source/drain structure are disposed over the dielectric substrate. The epitaxial source/drain structure includes an inner portion having a first dopant concentration and an outer portion having a second dopant concentration that is less than the first dopant concentration. The inner portion physically contacts the dielectric substrate, and the outer portion is disposed between the inner portion and the channel layer. In some embodiments, the outer portion physically contacts the dielectric substrate.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: January 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Ming Lee, I-Wen Wu, Po-Yu Huang, Fu-Kai Yang, Mei-Yun Wang