Patents by Inventor Fu-Kang Chiao

Fu-Kang Chiao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Bump layout for coplanarity improvement
    Patent number: 11211318
    Abstract: A method includes receiving a first design for conductive bumps on a first surface of an interposer, the conductive bumps in the first design having a same cross-section area; grouping the conductive bumps in the first design into a first group of conductive bumps in a first region of the first surface and a second group of conductive bumps in a second region of the first surface, where a bump pattern density of the second region is lower than that of the first region; forming a second design by modifying the first design, where modifying the first design includes modifying a cross-section area of the second group of conductive bumps in the second region; and forming the conductive bumps on the first surface of the interposer in accordance with the second design, where after being formed, the first group of conductive bumps and the second group of conductive bumps have different cross-section areas.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: December 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ling-Wei Li, Cheng-Lin Huang, Min-Tar Liu, Fu-Kang Chiao, Matt Chou, Chun-Yen Lo, Che-Jung Chu, Wen-Ming Chen, Kuo-Chio Liu
  • BUMP LAYOUT FOR COPLANARITY IMPROVEMENT
    Publication number: 20200105654
    Abstract: A method includes receiving a first design for conductive bumps on a first surface of an interposer, the conductive bumps in the first design having a same cross-section area; grouping the conductive bumps in the first design into a first group of conductive bumps in a first region of the first surface and a second group of conductive bumps in a second region of the first surface, where a bump pattern density of the second region is lower than that of the first region; forming a second design by modifying the first design, where modifying the first design includes modifying a cross-section area of the second group of conductive bumps in the second region; and forming the conductive bumps on the first surface of the interposer in accordance with the second design, where after being formed, the first group of conductive bumps and the second group of conductive bumps have different cross-section areas.
    Type: Application
    Filed: June 21, 2019
    Publication date: April 2, 2020
    Inventors: Ling-Wei Li, Cheng-Lin Huang, Min-Tar Liu, Fu-Kang Chiao, Matt Chou, Chun-Yen Lo, Che-Jung Chu, Wen-Ming Chen, Kuo-Chio Liu