Patents by Inventor FU LIAO

FU LIAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230276031
    Abstract: A filter element and a projection device are provided. The filter element is configured on the transmission path of at least one light beam, and includes a substrate and a film. The film is located on a surface of the substrate, and includes a first area and a second area. The first area includes a center, corresponding to the central axis of the at least one light beam. The distance between the second area and the center of the first area is greater than the distance between any point in the first area and the center. The average thickness of the second area of the film is greater than the average thickness of the first area of the film. The filter element of the disclosure may still have a similar filter effect when the incident angle is relatively large.
    Type: Application
    Filed: February 23, 2023
    Publication date: August 31, 2023
    Applicant: Coretronic Corporation
    Inventors: Chi-Fu Liu, Tsung-Hsin Liao, Kun-Liang Jao, Hung-Yu Lin
  • Publication number: 20230274072
    Abstract: A method includes identifying a cell in the layout diagram as a violated cell that fails to pass one or more design rules related to IR drops, and classifying a root cause of the violated cell with a root cause class. The method also includes determining a searching area for searching safe region candidates, and finding a selected cell for moving based upon the root cause class of the root cause. The method further includes finding a safe region in the searching area for moving the selected cell, and moving the selected cell to the safe region if the safe region is found within the searching area.
    Type: Application
    Filed: March 10, 2022
    Publication date: August 31, 2023
    Inventors: Fa ZHOU, JinXin LIU, Chieh-Fu CHU, Yen-Feng SU, Chia-Chun LIAO, Meng-Hsuan WU, Dei-Pei LIU
  • Publication number: 20230262989
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC) comprising a first electrode structure disposed in a substrate. A first ferroelectric structure is disposed on a first side of the first electrode structure. A channel structure is disposed on a first side of the first ferroelectric structure. The channel structure includes a plurality of individual channel structures and a plurality of insulator structures. The plurality of individual channel structures and the plurality of insulator structures are alternately stacked. A pair of source/drain (S/D) structures are disposed on the first side of the first ferroelectric structure. The pair of S/D structures extend vertically through the channel structure, and the first electrode structure is disposed laterally between the S/D structures of the pair of S/D structures.
    Type: Application
    Filed: February 16, 2022
    Publication date: August 17, 2023
    Inventors: Yen-Chieh Huang, Po-Ting Lin, Song-Fu Liao, Hai-Ching Chen, Sai-Hooi Yeong, Yu-Ming Lin, Chung-Te Lin
  • Publication number: 20230253463
    Abstract: A method for manufacturing a semiconductor feature includes: alternatingly forming first and second dielectric layers on a semiconductor substrate along a vertical direction; forming multiple spaced-apart trenches penetrating the first and second dielectric layers; forming multiple support segments filling the trenches; removing the second dielectric layers to form multiple spaces; forming multiple conductive layers filling the spaces; removing the support segments to expose the conductive layers and the first dielectric layers; selectively forming a blocking layer covering the first dielectric layers outside of the conductive layers; forming multiple selectively-deposited sub-layers on the exposed conductive layers outside of the blocking layer and each connected to one of the conductive layers; forming multiple channel sub-layers on the selectively-deposited sub-layers outside of the blocking layer; removing the blocking layer; forming multiple isolation sub-layers filling the trenches; and forming multiple
    Type: Application
    Filed: April 14, 2023
    Publication date: August 10, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Song-Fu LIAO, Hai-Ching CHEN, Chung-Te LIN
  • Publication number: 20230249437
    Abstract: A windable display module and a display device. The display module includes a plurality of film layers stacked together and at least one connecting layer group arranged between the plurality of film layers. In a stacking direction, the at least one connecting layer group is in contact with its adjacent film layer, so that a variable connecting force is generated between the film layers that are adjacent to the at least one connecting layer group. During a winding process or an unwinding process of the display module, a first connecting force is generated between the film layers that are adjacent to the at least one connecting layer group. During a displaying process of the display module, a second connecting force is generated between at least parts of the film layers that are in a displaying region. The first connecting force is less than the second connecting force.
    Type: Application
    Filed: April 13, 2023
    Publication date: August 10, 2023
    Applicant: KunShan Go-Visionox Opto-Electronics Co., Ltd
    Inventors: Jia LIU, Liwei DING, Fu LIAO, Zheng LI, Xuebin LI
  • Publication number: 20230253256
    Abstract: A method includes forming a first gate dielectric, a second gate dielectric, and a third gate dielectric over a first semiconductor region, a second semiconductor region, and a third semiconductor region, respectively. The method further includes depositing a first lanthanum-containing layer overlapping the first gate dielectric, and depositing a second lanthanum-containing layer overlapping the second gate dielectric. The second lanthanum-containing layer is thinner than the first lanthanum-containing layer. An anneal process is then performed to drive lanthanum in the first lanthanum-containing layer and the second lanthanum-containing layer into the first gate dielectric and the second gate dielectric, respectively. During the anneal process, the third gate dielectric is free from lanthanum-containing layers thereon.
    Type: Application
    Filed: April 19, 2023
    Publication date: August 10, 2023
    Inventors: Wen-Hung Huang, Kuo-Feng Yu, Jian-Hao Chen, Shan-Mei Liao, Jer-Fu Wang, Yung-Hsiang Chan
  • Publication number: 20230255026
    Abstract: Disposed are a semiconductor structure, a manufacturing method thereof and a flash memory. The semiconductor structure includes a substrate, first isolation structures, a gate structure and an oxide layer. The first isolation structures define a first active area in a peripheral region of the substrate. The oxide layer is disposed on the substrate in the first active area and covered by the first isolation structures. The oxide layer and the first isolation structures define an opening exposing the substrate. The gate structure is disposed on the substrate in the first active area and includes a gate dielectric layer disposed in the opening and a gate disposed on the gate dielectric layer. The oxide layer is located around the gate dielectric layer. The width of the bottom surface of the gate is less than that of the top surface of the first active area.
    Type: Application
    Filed: April 10, 2023
    Publication date: August 10, 2023
    Applicant: Winbond Electronics Corp.
    Inventors: Yao-Ting Tsai, Hsiu-Han Liao, Che-Fu Chuang
  • Publication number: 20230244278
    Abstract: A display module and a display device. The display module includes: a display panel including a display surface and a non-display surface arranged opposite to each other; a support layer arranged on the non-display surface of the display panel, the support layer having a first surface away from the display panel, and at least part of the first surface is provided with a first shape portion arranged in a predetermined direction; and a rotating shaft having a second shape portion in a circumferential direction, the support layer and the display panel arranged around an outer circumference of the rotating shaft, the first shape portion of the first surface engaged with the second shape portion of the rotating shaft.
    Type: Application
    Filed: April 7, 2023
    Publication date: August 3, 2023
    Applicant: KunShan Go-Visionox Opto-Electronics Co., Ltd
    Inventors: Desong YAN, Fu LIAO, Liwei DING, Yongfeng ZHAO, Hongqi HOU, Zheng LI
  • Publication number: 20230247841
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC) comprising a lower gate electrode disposed in a dielectric structure. A first ferroelectric structure overlies the lower gate electrode. A first floating electrode structure overlies the first ferroelectric structure. A channel structure overlies the first floating electrode structure. A second floating electrode structure overlies the channel structure. A second ferroelectric structure overlies the second floating electrode structure. An upper gate electrode overlies the second ferroelectric structure.
    Type: Application
    Filed: February 2, 2022
    Publication date: August 3, 2023
    Inventors: Yen-Chieh Huang, Po-Ting Lin, Song-Fu Liao, Hai-Ching Chen, Sai-Hooi Yeong, Yu-Ming Lin, Chung-Te Lin
  • Publication number: 20230240024
    Abstract: A method for adjusting the uniformity of a display is provided. The method includes the following steps. An angle sensor is disposed on a display. The display opposite to a measurement device is disposed on a rotation axis. The uniformity of a frame of the display at at least one use angle is measured by the measurement device, wherein the display is adjusted to a first use angle and is left still for a period of time, so that the uniformity of the display arranged at the first use angle has a first uniformity correction parameter; and a correspondence table relevant to the first use angle and the first uniformity correction parameter is stored to the display.
    Type: Application
    Filed: March 25, 2022
    Publication date: July 27, 2023
    Applicant: Qisda Corporation
    Inventors: Yi-Wen CHIOU, Shih-Yao LIN, Chun-Fu CHEN, Lung-Li CHUNG, Chen-Ning LIAO
  • Publication number: 20230229191
    Abstract: Support structural members, which are used in a flexible display panel. The support structural members comprise a main body support member, which includes a bearing part used for bearing a portion of the flexible display panel; a sliding support member, which is connected to the main body support member in a manner that allows movement along a second direction, the sliding support member includes a first support part and a second support part which are distributed at an interval along a first direction, the first support part being used for extending the main body support member and jointly supporting the flexible display panel with the bearing part; a pushing member, which is connected to the second support part in a manner that allows movement along the second direction, the pushing member includes a stopping part.
    Type: Application
    Filed: March 27, 2023
    Publication date: July 20, 2023
    Applicant: KunShan Go-Visionox Opto-Electronics Co., Ltd
    Inventors: Yongfeng ZHAO, Fan DONG, Liwei DING, Fu LIAO, Hongqi HOU, Zheng LI
  • Publication number: 20230214493
    Abstract: A computer system for failing a secure boot in a case tampering event comprises a trusted platform module (TPM), for generating a plurality of random bytes for a secure boot of the computer system; a bootloader, for storing information in at least one hardware of the computer system and performing the secure boot, wherein the information comprises the plurality of random bytes, and the TPM is comprised in the bootloader; an operating system (OS), for performing the secure boot; and at least one sensor, for detecting a case tampering event in the computer system, and transmitting a signal for triggering a deletion of the plurality of random bytes, if the case tampering event happens in the computer system. The bootloader or the OS performs the operation of deleting the plurality of random bytes stored in the at least one hardware to fail the secure boot, in response to the signal.
    Type: Application
    Filed: December 30, 2021
    Publication date: July 6, 2023
    Applicant: Moxa Inc.
    Inventors: YOONG TAK TAN, Chih-Yu Chen, Che-Yu Huang, Hsin-Ju Wu, Tsung-Yuan Wu, Tzung-Fu Tsai, Kuo-Chen Wu, Jian-Yu Liao, Tsung-Li Fang
  • Publication number: 20230209820
    Abstract: Provided are a memory device and a method of manufacturing the same. The memory device includes: a stack structure; a first source/drain region and a second source/drain region located in a substrate beside the stack structure; a first self-aligned contact connected to the first source/drain region; a second self-aligned contact connected to the second source/drain region; a first liner structure located between the first self-aligned contact and a first sidewall of the stack structure; and a second liner structure located between the second self-aligned contact and a second sidewall of the stack structure. The first liner structure and the second liner structure are not connected and do not cover the stack structure.
    Type: Application
    Filed: December 29, 2021
    Publication date: June 29, 2023
    Applicant: Winbond Electronics Corp.
    Inventors: Che-Fu Chuang, Yao-Ting Tsai, Hsiu-Han Liao
  • Patent number: 11690228
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first conductive structure arranged over a substrate. A memory layer is arranged over the first conductive structure, below a second conductive structure, and includes a ferroelectric material. An annealed seed layer is arranged between the first and second conductive structures and directly on a first side of the memory layer. An amount of the crystal structure that includes an orthorhombic phase is greater than about 35 percent.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: June 27, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Song-Fu Liao, Rainer Yen-Chieh Huang, Hai-Ching Chen, Chung-Te Lin
  • Publication number: 20230199092
    Abstract: A foldable structural member and a display device. The foldable structural member includes a structural main body including a first main body and a second main body distributed in a first direction, and a bending portion located between the first main body and the second main body, in which the foldable structural member is enabled to be switched between an unfolding state and a folding state by the bending portion, a buckle assembly, including a first buckle piece and a second buckle piece engaged with the first buckle piece, in which the first buckle piece is arranged on the first main body, and the second buckle piece is arranged on the second main body, in an inward-folding state or an outward-folding state, the first buckle piece is buckled with the second buckle piece to connect the first main body with the second main body.
    Type: Application
    Filed: February 14, 2023
    Publication date: June 22, 2023
    Applicant: KunShan Go-Visionox Opto-Electronics Co., Ltd
    Inventors: Hongqi HOU, Liwei DING, Fu LIAO, Yuhua WU, Zhaoji ZHU, Kanglong SUN
  • Publication number: 20230199091
    Abstract: A foldable support member and a display device. The foldable support member has a folding state and an unfolding state. The foldable support member includes a rotating shaft portion including a fixing shaft formed by extending in a first direction and a rotating assembly rotatably connected to the fixing shaft, a support plate including a connecting portion and an unfolding portion connected to the connecting portion, in which the connecting portion is fixed to the fixing shaft and the unfolding portion is arranged to be foldable around the fixing shaft relative to the connecting portion. The unfolding portion is slidably connected to the rotating assembly in a circumferential direction of the fixing shaft, and the unfolding portion is slidable in the circumferential direction along the rotating assembly when the foldable support member is switched between the folding state and the unfolding state.
    Type: Application
    Filed: February 15, 2023
    Publication date: June 22, 2023
    Applicant: KunShan Go-Visionox Opto-Electronics Co., Ltd
    Inventors: Hongqi HOU, Liwei DING, Fu LIAO, Zhaoji ZHU, Yuhua WU, Kanglong SUN
  • Publication number: 20230188631
    Abstract: A support structural member and a display device. The support structural member comprises a support frame, a screen body fixture, a screen body connector and a power assembly. The support frame comprises a first support body and a second support body movably connected to the first support body in a first direction. The screen body fixture is connected to the first support body. The screen body connector is configured to guide a screen body to be unfolded or folded. The screen body connector is movably connected to the second support body. The second support body and the screen body connector are both connected to the power assembly, the power assembly drives the second support body to protrude or retract relative to the first support body, and enables the screen body connector and the second support body to move simultaneously in the first direction.
    Type: Application
    Filed: February 10, 2023
    Publication date: June 15, 2023
    Applicant: KunShan Go-Visionox Opto-Electronics Co., Ltd
    Inventors: Hongqi HOU, Liwei DING, Fu LIAO, Yuhua WU, Zhaoji ZHU, Kanglong SUN
  • Publication number: 20230184567
    Abstract: The differential capacitor device includes a differential capacitor sensing component, a calibration capacitor assembly and two output terminals. The differential capacitive sensing element has a common point terminal, a first non-common point terminal and a second non-common point terminal, and the common point terminal is configured to receive an input voltage. The calibration capacitor assembly has a first calibration capacitor and a second calibration capacitor, one terminal of the calibration capacitor assembly is coupled to the first non-common point terminal and the second non-common point terminal, and the other terminal of the calibration capacitor assembly is configured to receive a first calibration voltage and a second calibration voltage. The two output terminals are respectively coupled to the first non-common point terminal and the second non-common point terminal to output a first signal and a second signal.
    Type: Application
    Filed: July 12, 2022
    Publication date: June 15, 2023
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Lu-Po LIAO, Chin-Fu KUO, Liang-Ying LIU, Yu-Sheng LIN
  • Publication number: 20230185280
    Abstract: An integrated circuit (IC) configurable to perform adaptive thermal ceiling control in a per-functional-block manner, an associated main circuit, an associated electronic device and an associated thermal control method are provided. The IC may include a plurality of hardware circuits arranged to perform operations of a first functional block, and at least one thermal control circuit. At least one temperature sensor is coupled with the first functional block to detect temperature and to generate at least one temperature sensing result of the first functional block.
    Type: Application
    Filed: November 23, 2022
    Publication date: June 15, 2023
    Applicant: MEDIATEK INC.
    Inventors: Chih-Fu Tsai, Yu-Chia Chang, Bo-Jiun Yang, Yen-Hwei Hsieh, Shun-Yao Yang, Jia-Wei Fang, Ta-Chang Liao, Tai-Yu Chen
  • Patent number: 11678484
    Abstract: Disposed are a semiconductor structure, a manufacturing method thereof and a flash memory. The semiconductor structure includes a substrate, first isolation structures, a gate structure and an oxide layer. The first isolation structures define a first active area in a peripheral region of the substrate. The oxide layer is disposed on the substrate in the first active area and covered by the first isolation structures. The oxide layer and the first isolation structures define an opening exposing the substrate. The gate structure is disposed on the substrate in the first active area and includes a gate dielectric layer disposed in the opening and a gate disposed on the gate dielectric layer. The oxide layer is located around the gate dielectric layer. The width of the bottom surface of the gate is less than that of the top surface of the first active area.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: June 13, 2023
    Assignee: Winbond Electronics Corp.
    Inventors: Yao-Ting Tsai, Hsiu-Han Liao, Che-Fu Chuang