Patents by Inventor Fu Ming Huang

Fu Ming Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190268050
    Abstract: A communication device includes a smart antenna, a storage device, and a processor. The smart antenna is capable of switching between a plurality of antenna modes. In each of the antenna modes during a training stage, the smart antenna receives a first feedback datum, and the processor calculates a reward indicator according to the first feedback datum. The processor compares all of the reward indicators with each other and controls the smart antenna to select a specific mode of the antenna modes according to a comparison between all of the reward indicators. In the specific mode, the smart antenna receives a second feedback datum, the processor determines the weight function of the first feedback datum and the second feedback datum of the specific mode, and the processor updates the reward indicator of the specific mode according to the weight function.
    Type: Application
    Filed: February 27, 2018
    Publication date: August 29, 2019
    Inventors: Huai-Ming CHANG, Tsun-Che HUANG, Yu TAO, Fu-Ming KANG
  • Patent number: 10381306
    Abstract: A semiconductor memory device and a manufacturing method thereof are provided in the present invention. An under-cut structure is formed at an edge of a bit line contact opening in the process of forming the bit line contact opening for avoiding short problems caused by alignment shifting, and the process window of the process of forming the bit line contact opening may be improved accordingly.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: August 13, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Shih-Fang Tzou, Fu-Che Lee, Chien-Cheng Tsai, Feng-Ming Huang
  • Publication number: 20190244804
    Abstract: A method includes performing a first post Chemical Mechanical Polish (CMP) cleaning on a wafer using a first brush. The first brush rotates to clean the wafer. The method further includes performing a second post-CMP cleaning on the wafer using a second brush. The second brush rotates to clean the wafer. The first post-CMP cleaning and the second post-CMP cleaning are performed simultaneously.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 8, 2019
    Inventors: Fu-Ming Huang, Liang-Guang Chen, Ting-Kui Chang, Chun-Chieh Lin
  • Patent number: 10361287
    Abstract: A method of manufacturing a semiconductor device includes receiving a FinFET precursor including a fin structure formed between some isolation regions, and a gate structure formed over a portion of the fin structure; removing a top portion of the fin structure on either side of the gate structure; growing a semiconductive layer on top of a remaining portion of the fin structure such that a plurality of corners is formed over the fin structure; forming a capping layer over the semiconductive layer; performing an annealing process on the FinFET precursor to form a plurality of dislocations proximate to the corners; and removing the capping layer.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: July 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: I-Chih Chen, Chih-Ming Hsieh, Fu-Tsun Tsai, Yung-Fa Lee, Chih-Mu Huang
  • Patent number: 10269555
    Abstract: A method includes performing a first post Chemical Mechanical Polish (CMP) cleaning on a wafer using a first brush. The first brush rotates to clean the wafer. The method further includes performing a second post-CMP cleaning on the wafer using a second brush. The second brush rotates to clean the wafer. The first post-CMP cleaning and the second post-CMP cleaning are performed simultaneously.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fu-Ming Huang, Liang-Guang Chen, Ting-Kui Chang, Chun-Chieh Lin
  • Patent number: 10062645
    Abstract: An interconnect and a method of forming an interconnect for a semiconductor device is provided. The interconnect is formed by treating an upper surface of a dielectric layer to create a high density layer. The treatment may include, for example, creating a high density monolayer using hexamethyldisilazane (HMDS), trimethylsilydiethylamine (TMSDEA) or trimethylsilylacetate (OTMSA). After treating, the dielectric layer may be patterned to create openings, which are subsequently filled with a conductive material. Excess conductive material may be removed using, for example, a chemical mechanical polishing.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: August 28, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Han-Hsin Kuo, Chung-Chi Ko, Neng-Jye Yang, Fu-Ming Huang, Chi-Ming Tsai, Liang-Guang Chen
  • Patent number: 9962805
    Abstract: A polisher head of a polishing apparatus includes a membrane and a first local pressure nodule and a second local pressure nodule physically contacting the membrane. The first local pressure nodule is configured to apply a first local force to the membrane and the second local pressure nodule is configured to apply a second local force to the membrane. The first local pressure nodule and the second local pressure nodule are independently controllable.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: May 8, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Kui Chang, Fu-Ming Huang, Liang-Guang Chen, Chun-Chieh Lin
  • Publication number: 20170304990
    Abstract: A polisher head of a polishing apparatus includes a membrane and a first local pressure nodule and a second local pressure nodule physically contacting the membrane. The first local pressure nodule is configured to apply a first local force to the membrane and the second local pressure nodule is configured to apply a second local force to the membrane. The first local pressure nodule and the second local pressure nodule are independently controllable.
    Type: Application
    Filed: April 22, 2016
    Publication date: October 26, 2017
    Inventors: Ting-Kui Chang, Fu-Ming Huang, Liang-Guang Chen, Chun-Chieh Lin
  • Publication number: 20170278785
    Abstract: An interconnect and a method of forming an interconnect for a semiconductor device is provided. The interconnect is formed by treating an upper surface of a dielectric layer to create a high density layer. The treatment may include, for example, creating a high density monolayer using hexamethyldisilazane (HMDS), trimethylsilydiethylamine (TMSDEA) or trimethylsilylacetate (OTMSA). After treating, the dielectric layer may be patterned to create openings, which are subsequently filled with a conductive material. Excess conductive material may be removed using, for example, a chemical mechanical polishing.
    Type: Application
    Filed: June 12, 2017
    Publication date: September 28, 2017
    Inventors: Han-Hsin Kuo, Chung-Chi Ko, Neng-Jye Yang, Fu-Ming Huang, Chi-Ming Tsai, Liang-Guang Chen
  • Patent number: 9723915
    Abstract: A method for cleaning a brush includes inducing a static charge on a surface of a first plate, wherein the first plate comprises at least one of silicon nitride (SixNy) or silicon oxide (SiaOb), wherein a, b, x and y are integers. The method further includes rotating the brush in contact with the surface of the first plate.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: August 8, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Fu-Ming Huang, Liang-Guang Chen, Han-Hsin Kuo, Chi-Ming Tsai, He Hui Peng
  • Patent number: 9679848
    Abstract: An interconnect and a method of forming an interconnect for a semiconductor device is provided. The interconnect is formed by treating an upper surface of a dielectric layer to create a high density layer. The treatment may include, for example, creating a high density monolayer using hexamethyldisilazane (HMDS), trimethylsilydiethylamine (TMSDEA) or trimethylsilylacetate (OTMSA). After treating, the dielectric layer may be patterned to create openings, which are subsequently filled with a conductive material. Excess conductive material may be removed using, for example, a chemical mechanical polishing.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: June 13, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Han-Hsin Kuo, Chung-Chi Ko, Neng-Jye Yang, Fu-Ming Huang, Chi-Ming Tsai, Liang-Guang Chen
  • Patent number: 9630295
    Abstract: Embodiments of mechanisms for performing a chemical mechanical polishing (CMP) process are provided. A method for performing a CMP process includes polishing a wafer by using a polishing pad. The method also includes applying a cleaning liquid jet on the polishing pad to condition the polishing pad. A CMP system is also provided.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: April 25, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: He-Hui Peng, Fu-Ming Huang, Shich-Chang Suen, Han-Hsin Kuo, Chi-Ming Tsai, Liang-Guang Chen
  • Publication number: 20170092481
    Abstract: A method includes performing a first post Chemical Mechanical Polish (CMP) cleaning on a wafer using a first brush. The first brush rotates to clean the wafer. The method further includes performing a second post-CMP cleaning on the wafer using a second brush. The second brush rotates to clean the wafer. The first post-CMP cleaning and the second post-CMP cleaning are performed simultaneously.
    Type: Application
    Filed: September 30, 2015
    Publication date: March 30, 2017
    Inventors: Fu-Ming Huang, Liang-Guang Chen, Ting-Kui Chang, Chun-Chieh Lin
  • Publication number: 20170018496
    Abstract: An interconnect and a method of forming an interconnect for a semiconductor device is provided. The interconnect is formed by treating an upper surface of a dielectric layer to create a high density layer. The treatment may include, for example, creating a high density monolayer using hexamethyldisilazane (HMDS), trimethylsilydiethylamine (TMSDEA) or trimethylsilylacetate (OTMSA). After treating, the dielectric layer may be patterned to create openings, which are subsequently filled with a conductive material. Excess conductive material may be removed using, for example, a chemical mechanical polishing.
    Type: Application
    Filed: September 30, 2016
    Publication date: January 19, 2017
    Inventors: Han-Hsin Kuo, Chung-Chi Ko, Neng-Jye Yang, Fu-Ming Huang, Chi-Ming Tsai, Liang-Guang Chen
  • Patent number: 9460997
    Abstract: An interconnect and a method of forming an interconnect for a semiconductor device is provided. The interconnect is formed by treating an upper surface of a dielectric layer to create a high density layer. The treatment may include, for example, creating a high density monolayer using hexamethyldisilazane (HMDS), trimethylsilydiethylamine (TMSDEA) or trimethylsilylacetate (OTMSA). After treating, the dielectric layer may be patterned to create openings, which are subsequently filled with a conductive material. Excess conductive material may be removed using, for example, a chemical mechanical polishing.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: October 4, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Han-Hsin Kuo, Chung-Chi Ko, Neng-Jye Yang, Fu-Ming Huang, Chi-Ming Tsai, Liang-Guang Chen
  • Patent number: 9370854
    Abstract: The present disclosure provides a method of fabricating a semiconductor device with metal interconnections and a design of a tool for performing such a method. In one embodiment, a method of fabricating a semiconductor device, the method includes providing a semiconductor substrate, depositing a dielectric layer over the semiconductor substrate, forming at least one trench in the dielectric layer, and forming a metallization layer in the trench and over the dielectric layer. The method further includes performing a chemical mechanical polishing process to planarize the metallization layer and the dielectric layer, performing a surface treatment on the planarized dielectric layer to form a protection layer, cleaning the planarized metallization layer and the treated dielectric layer to remove residue from the chemical mechanical polishing process, and drying the cleaned metallization layer and dielectric layer in an inert gas environment.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: June 21, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Han-Hsin Kuo, Fu-Ming Huang
  • Patent number: 9305880
    Abstract: A semiconductor substructure with improved performance and a method of forming the same is described. The method includes providing a semiconductor dielectric layer having a recess formed therein; forming an interconnect structure with a metal liner and a conductive fill within the recess; and applying an electron beam treatment to the substructure.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: April 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fu-Ming Huang, Han-Hsin Kuo, Chi-Ming Tsai, Liang-Guang Chen
  • Patent number: 9252060
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate and an interconnect structure disposed over the substrate. The interconnect structure includes a plurality of interconnect layers. One of the interconnect layers contains: a plurality of metal via slots and a bulk metal component disposed over the plurality of metal via slots. The present disclosure also provides a method. The method includes providing a wafer, and forming a first layer over the wafer. The method includes forming an interconnect structure over the first layer. The forming the interconnect structure includes forming a second interconnect layer over the first layer, and forming a third interconnect layer over the second interconnect layer. The second interconnect layer is formed to contain a plurality of metal via slots and a bulk metal component formed over the plurality of metal via slots. The third interconnect layer contains one or more metal trenches.
    Type: Grant
    Filed: April 1, 2012
    Date of Patent: February 2, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Ming Tsai, Liang-Guang Chen, Han-Hsin Kuo, Fu-Ming Huang, Hao-Jen Liao, Ming-Chung Liang
  • Publication number: 20150335146
    Abstract: A method for cleaning a brush includes inducing a static charge on a surface of a first plate, wherein the first plate comprises at least one of silicon nitride (SixNy) or silicon oxide (SiaOb), wherein a, b, x and y are integers. The method further includes rotating the brush in contact with the surface of the first plate.
    Type: Application
    Filed: August 4, 2015
    Publication date: November 26, 2015
    Inventors: Fu-Ming HUANG, Liang-Guang CHEN, Han-Hsin KUO, Chi-Ming TSAI, He Hui PENG
  • Patent number: 9119464
    Abstract: A brush cleaning system comprising: a plate comprising at least one of silicon nitride (SixNy) or silicon oxide (SiaOb), wherein the plate has a static charge on a surface thereof; and a machine configured to rotate a brush in contact with the static charged surface of the plate.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: September 1, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Fu-Ming Huang, Liang-Guang Chen, Han-Hsin Kuo, Chi-Ming Tsai, He Hui Peng