Abstract: A federated learning method includes: providing importance parameters and performance parameters by client devices respectively to a central device, performing a training procedure by the central device, wherein the training procedure includes: selecting target devices from the client devices according to a priority order associated with the importance parameters, dividing the target devices into training groups according to a similarity of the performance parameters, notifying the target devices to perform iterations according to the training groups respectively to generate trained models, transmitting the trained models to the central device, and updating a global model based on the trained models, performing the training procedure again or outputting the global model to the client devices based on a convergence value of the global model and the number of times of performing the training procedure.

Abstract: The disclosure provides an electronic device, including a circuit board, multiple semiconductor components, a first light reflecting structure, and a second light reflecting structure. The circuit board includes a substrate, and the substrate may have a first surface and at least one side surface. The multiple semiconductor components are disposed on the first surface. The first light reflecting structure is disposed on the first surface. The second light reflecting structure is disposed on the first surface and the at least one side surface.

Abstract: A propagation delay balance circuit includes a signal generating circuit, a path switching element, and a signal change detecting element. The signal generating circuit includes delay chains for outputting delay signals respectively. The path switching element has input terminals and output terminals. Each output terminal of the path switching element is electrically connected to the input terminal of each delay chain one-to-one, and input terminals of the path switching element are electrically connected one-to-one to the output terminals of the delay chains. The path switching element is controlled by the path switching controlling signal to change the one-to-one internal electrical connection between input terminals and output terminals of the path switching element. The signal change detecting element is electrically connected to the path switching element, and generates a path switching controlling signal according to delay signals of the path switching element.

Abstract: A propagation delay balance circuit includes a signal generating circuit, a path switching element, and a signal change detecting element. The signal generating circuit includes delay chains for outputting delay signals respectively. The path switching element has input terminals and output terminals. Each output terminal of the path switching element is electrically connected to the input terminal of each delay chain one-to-one, and input terminals of the path switching element are electrically connected one-to-one to the output terminals of the delay chains. The path switching element is controlled by the path switching controlling signal to change the one-to-one internal electrical connection between input terminals and output terminals of the path switching element. The signal change detecting element is electrically connected to the path switching element, and generates a path switching controlling signal according to delay signals of the path switching element.

Abstract: A capacitor cell for a semiconductor device, wherein the capacitor cell comprises: a capacitor having a first node and a second node; a first electrode structure, comprising a first contact point and a second contact point, wherein the first contact point and the second contact point are electrically connected to the first node of said capacitor and located at two different edges of the capacitor cell; and a second electrode structure, comprising a third contact point and a fourth contact point, wherein the third contact point and the fourth contact point are electrically connected to the second node of said capacitor and located at said two different edges of the capacitor cell.

Abstract: A capacitor cell for a semiconductor device, wherein the capacitor cell comprises: a capacitor having a first node and a second node; a first electrode structure, comprising a first contact point and a second contact point, wherein the first contact point and the second contact point are electrically connected to the first node of said capacitor and located at two different edges of the capacitor cell; and a second electrode structure, comprising a third contact point and a fourth contact point, wherein the third contact point and the fourth contact point are electrically connected to the second node of said capacitor and located at said two different edges of the capacitor cell.