Patents by Inventor Fu-To Lin
Fu-To Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240168371Abstract: Disclosed is a method of manufacturing a semiconductor device. The method includes forming a patterned hardmask over an underlying target layer on a substrate; and performing plasma fabrication operations in parallel on the patterned hardmask and underlying target layer in a plasma etching chamber using a plasma etch gas and a selective source gas. The plasma operations include forming a protective cap on the patterned hardmask; and removing portions of the underlying layer that are not covered by the patterned hardmask. In various embodiments, the selective source gas includes a chemical compound that includes a halogen gas that can be dissociated into a metal and a halogen, and the plasma operations include dissociating the metal and the halogen in the selective source gas and forming a protective cap on the patterned hardmask using the metal that has been dissociated.Type: ApplicationFiled: February 7, 2023Publication date: May 23, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuan-Da Huang, Chun-Fu Kuo, Yi Hsing Yu, Li-Te Lin
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Patent number: 11991482Abstract: An illumination system, a projection device, and a projection control method are provided. The illumination system includes a first light-emitting unit, a second light-emitting unit, a third light-emitting unit, a first dichroic element, a second dichroic element, and a control unit. The first light-emitting unit includes a first light-emitting element and a second light-emitting element. The control unit is electrically connected to the first light-emitting unit and configured to switch the illumination system between a high-performance mode and a high-chroma mode, wherein when the illumination system is in the high-performance mode, the control unit controls a current ratio of the second light-emitting element to be greater than a current ratio of the first light-emitting element, and when the illumination system is in the high-chroma mode, the control unit controls the current ratio of the second light-emitting element to be less than the current ratio of the first light-emitting element.Type: GrantFiled: October 28, 2022Date of Patent: May 21, 2024Assignee: Coretronic CorporationInventors: Chi-Fu Liu, Tsung-Hsin Liao, Chun-Li Chen, Hung-Yu Lin
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Publication number: 20240163768Abstract: A packet transmission method is provided. The packet transmission method may be applied to an apparatus. The packet transmission method may include the following steps. A path engine circuit of the apparatus may receive a packet from a modem circuit of the apparatus or from a Wi-Fi chip of the apparatus. Then, the path engine circuit may transmit the packet from the modem circuit to the Wi-Fi chip, or transmit the packet from the Wi-Fi chip to the modem circuit or a central processing unit (CPU) of the apparatus.Type: ApplicationFiled: November 8, 2023Publication date: May 16, 2024Inventors: Yen-Hsiung TSENG, Wei-Wen LIN, Chi-Fu KOH, Jyh-Ding HU, Hui-Ping TSENG
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Publication number: 20240161843Abstract: An anti-fuse memory device includes an anti-fuse module, a reference current circuit and a controller. A write enable signal enables a write controller and a write buffer of the anti-fuse module to program a selected anti-fuse memory cell in an anti-fuse array of the anti-fuse module, and a timing controller of the anti-fuse module stops a program operation of the anti-fuse array after a sense amplifier of the anti-fuse module changes a state of a readout data signal for a predetermined time duration.Type: ApplicationFiled: September 20, 2023Publication date: May 16, 2024Applicant: eMemory Technology Inc.Inventors: Chia-Fu Chang, Chun-Hung Lin, Jen-Yu Peng, You-Ruei Chuang
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Publication number: 20240164111Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first conductive structure arranged over a substrate. A memory layer is arranged over the first conductive structure, below a second conductive structure, and includes a ferroelectric material. An annealed seed layer is arranged between the first and second conductive structures and directly on a first side of the memory layer. An amount of the crystal structure that includes an orthorhombic phase is greater than about 35 percent.Type: ApplicationFiled: January 23, 2024Publication date: May 16, 2024Inventors: Song-Fu Liao, Rainer Yen-Chieh Huang, Hai-Ching Chen, Chung-Te Lin
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Patent number: 11985906Abstract: A magnetic tunnel junction (MTJ) memory cell and a metallic etch mask portion are formed over a substrate. At least one dielectric etch stop layer is deposited over the metallic etch mask portion, and a via-level dielectric layer is deposited over the at least one dielectric etch stop layer. A via cavity may be etched through the via-level dielectric layer, and a top surface of the at least one dielectric etch stop layer is physically exposed. The via cavity may be vertically extended by removing portions of the at least one dielectric etch stop layer and the metallic etch mask portion. A contact via structure is formed directly on a top surface of the top electrode in the via cavity to provide a low-resistance contact to the top electrode.Type: GrantFiled: March 12, 2021Date of Patent: May 14, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yu-Feng Yin, Tai-Yen Peng, An-Shen Chang, Han-Ting Tsai, Qiang Fu, Chung-Te Lin
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Patent number: 11984379Abstract: Provided is an electronic package, in which a heat dissipating body is formed on an electronic device and is combined with a heat sink so that the electronic device, the heat dissipating body and the heat sink form a receiving space, and a heat dissipating material is formed in the receiving space and in contact with the heat sink and the electronic device, where a fluid regulating space is formed between the heat dissipating material and the heat dissipating body and is used as a volume regulating space for the heat dissipating material during thermal expansion and contraction.Type: GrantFiled: July 8, 2021Date of Patent: May 14, 2024Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Yu-Lung Huang, Chih-Ming Huang, Kuo-Hua Yu, Chang-Fu Lin
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Integration scheme for breakdown voltage enhancement of a piezoelectric metal-insulator-metal device
Patent number: 11984261Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a dielectric structure sandwiched between a first electrode and a bottom electrode. A passivation layer overlies the second electrode and the dielectric structure. The passivation layer comprises a horizontal surface vertically below a top surface of the passivation layer. The horizontal surface is disposed above a top surface of the dielectric structure.Type: GrantFiled: August 25, 2021Date of Patent: May 14, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Anderson Lin, Chun-Ren Cheng, Chi-Yuan Shih, Shih-Fen Huang, Yi-Chuan Teng, Yi Heng Tsai, You-Ru Lin, Yen-Wen Chen, Fu-Chun Huang, Fan Hu, Ching-Hui Lin, Yan-Jie Liao -
Patent number: 11978740Abstract: A layer stack including a first bonding dielectric material layer, a dielectric metal oxide layer, and a second bonding dielectric material layer is formed over a top surface of a substrate including a substrate semiconductor layer. A conductive material layer is formed by depositing a conductive material over the second bonding dielectric material layer. The substrate semiconductor layer is thinned by removing portions of the substrate semiconductor layer that are distal from the layer stack, whereby a remaining portion of the substrate semiconductor layer includes a top semiconductor layer. A semiconductor device may be formed on the top semiconductor layer.Type: GrantFiled: February 17, 2022Date of Patent: May 7, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Harry-Hak-Lay Chuang, Kuo-Ching Huang, Wei-Cheng Wu, Hsin Fu Lin, Henry Wang, Chien Hung Liu, Tsung-Hao Yeh, Hsien Jung Chen
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Patent number: 11978392Abstract: A precharge method for a data driver includes steps of: outputting a display data to a plurality of output terminals of the data driver; outputting a second precharge voltage to an output terminal among the plurality of output terminals prior to outputting the display data to the output terminal, to precharge the output terminal to a voltage level closer to an output voltage; and outputting a first precharge voltage to the output terminal prior to outputting the second precharge voltage. The first precharge voltage provides a faster voltage transition on the output terminal than the second precharge voltage.Type: GrantFiled: May 31, 2023Date of Patent: May 7, 2024Assignee: NOVATEK Microelectronics Corp.Inventors: Min-Yang Chiu, Yu-Sheng Ma, Jin-Yi Lin, Hsuan-Yu Chen, Jhih-Siou Cheng, Chun-Fu Lin
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Publication number: 20240145163Abstract: A transformer includes a bobbin and a plurality of coils wound on the bobbin. The plurality of coils includes a first primary coil; a second primary coil, located above the first primary coil and electrically connected to the first primary coil; a secondary coil, located between the first primary coil and the second primary; a first auxiliary coil, located above the second primary coil; and a second auxiliary coil, located on the first auxiliary coil and electrically connected to the first auxiliary coil.Type: ApplicationFiled: October 20, 2023Publication date: May 2, 2024Inventors: Chiao FU, Yi-Chao LIN, Yao-Zhong LIU, Jia-Tay KUO
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Publication number: 20240144862Abstract: An electronic device with a first region and a second region located around the first region is disclosed. The electronic device includes a first gate driver and a second gate driver disposed in the second region, and a first transistor and a second transistor disposed in the first region. The first gate driver is used for outputting a first signal. The second gate driver is used for outputting a second signal. The first transistor is used for receiving the first signal from the first gate driver. The second transistor is used for receiving the second signal from the second gate driver. In a top view of the electronic device, the first region has a first side and a second side opposite to the first side, and the first gate driver and the second gate driver are located more adjacent to the first side and away from the second side.Type: ApplicationFiled: January 3, 2024Publication date: May 2, 2024Applicant: InnoLux CorporationInventors: Chun-Hsien LIN, Jui-Feng KO, Geng-Fu CHANG
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Publication number: 20240145498Abstract: Some embodiments relate to an integrated chip including a substrate having a first side and a second side opposite the first side. The integrated chip further includes a first photodetector positioned in a first pixel region within the substrate. A floating diffusion region with a first doping concentration of a first polarity is positioned on the first side of the substrate in the first pixel region. A first body contact region with a second doping concentration of a second polarity different from the first polarity is positioned on the second side of the substrate in the first pixel region.Type: ApplicationFiled: January 4, 2023Publication date: May 2, 2024Inventors: Hao-Lin Yang, Fu-Sheng Kuo, Ching-Chun Wang, Hsiao-Hui Tseng, Tzu-Jui Wang, Chen-Jong Wang, Dun-Nian Yaung
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Patent number: 11973014Abstract: Provided is a substrate structure including a substrate body, electrical contact pads and an insulating protection layer disposed on the substrate body, wherein the insulating protection layer has openings exposing the electrical contact pads, and at least one of the electrical contact pads has at least a concave portion filled with a filling material to prevent solder material from permeating along surfaces of the insulating protection layer and the electric contact pads, thereby eliminating the phenomenon of solder extrusion. Thus, bridging in the substrate structure can be eliminated even when the bump pitch between two adjacent electrical contact pads is small. As a result, short circuits can be prevented, and production yield can be increased.Type: GrantFiled: November 21, 2019Date of Patent: April 30, 2024Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chang-Fu Lin, Chin-Tsai Yao, Chun-Tang Lin, Fu-Tang Huang
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Patent number: 11972363Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for obtaining a plurality of model representations of predictive models, each model representation associated with a respective user and expresses a respective predictive model, and selecting a model implementation for each of the model representations based on one or more system usage properties associated with the user associated with the corresponding model representation.Type: GrantFiled: May 22, 2020Date of Patent: April 30, 2024Assignee: Google LLCInventors: Wei-Hao Lin, Travis H. K. Green, Robert Kaplow, Gang Fu, Gideon S. Mann
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Patent number: 11973502Abstract: A circuit includes cross coupled invertors including a first invertor and a second inventor. The first invertor and the second invertor are cross coupled at a first data node and a second data node. An input unit is coupled between the cross-coupled invertors and a power node. The input unit controls the cross-coupled invertors in response to a first input signal received at a first input terminal of the input unit and a second input signal received at a second input terminal of the input unit. A first transistor is connected between the power node and a supply node. The first transistor connects the power node to the supply node in response to an enable signal changing to a first value. A second transistor is connected between the power node and ground. The second transistor connects the power node to the ground in response to the enable signal changing to a second value.Type: GrantFiled: May 1, 2023Date of Patent: April 30, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Fu Lee, Hon-Jarn Lin, Yu-Der Chih
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Publication number: 20240133716Abstract: A reading device for capacitive sensing element comprises a differential capacitive sensing element, a modulator, a charge-voltage conversion circuit, a phase adjustment circuit, a demodulator and a low-pass filter. The modulator outputs a modulation signal to the common node of the capacitive sensing element and modulates the output signal of the capacitive sensing element. The two input terminals of the charge-to-voltage conversion circuit are connected to two non-common nodes of the capacitive sensing element. The charge-to-voltage converter read the output charge of the capacitive sensing element and convert it into a voltage signal. The modulator generates a demodulation signal through the phase adjustment circuit. The demodulator receives the demodulation signal from the phase adjustment circuit and demodulates the output of the charge-to-voltage conversion circuit. The low-pass filter is connected to the output of the demodulator for filtering the demodulated voltage signal to output the read signal.Type: ApplicationFiled: January 13, 2023Publication date: April 25, 2024Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Lu-Pu LIAO, Yu-Sheng LIN, Liang-Ying LIU, Chin-Fu KUO
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Publication number: 20240136463Abstract: This disclosure discloses an optical sensing device. The device includes a carrier body; a first light-emitting device disposed on the carrier body; and a light-receiving device including a group III-V semiconductor material disposed on the carrier body, including a light-receiving surface having an area, wherein the light-receiving device is capable of receiving a first received wavelength having a largest external quantum efficiency so the ratio of the largest external quantum efficiency to the area is ?13.Type: ApplicationFiled: December 20, 2023Publication date: April 25, 2024Applicant: EPISTAR CORPORATIONInventors: Yi-Chieh LIN, Shiuan-Leh LIN, Yung-Fu CHANG, Shih-Chang LEE, Chia-Liang HSU, Yi HSIAO, Wen-Luh LIAO, Hong-Chi SHIH, Mei-Chun LIU
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Patent number: 11964220Abstract: The present invention provides a hydrophilic/oleophobic sponge, a preparation method and use thereof, and belongs to the technical field of functional material preparation. In the present invention, a modified solution is obtained by mixing a nanoparticle suspension with a modifier solution; the nanoparticle suspension includes silica-encapsulated Fe3O4 nanoparticle suspension and/or nano-silica ethanol suspension; the modifier solution includes chitosan-acetic acid aqueous solution and polyvinyl alcohol (PVA) aqueous solution. The sponge is soaked in the modified solution, mixed and crosslinked with glutaraldehyde aqueous solution to obtain the hydrophilic/oleophobic sponge, conferring good oil-water separation ability on the sponge. The sponge effectively separates a heavy water layer from oil-water mixtures with such light oils as lubricating oil, engine oil, pump oil, crude oil, gasoline, and sunflower seed oil in a simple gravity-driven manner.Type: GrantFiled: June 18, 2019Date of Patent: April 23, 2024Assignee: Guangdong University of Petrochemical TechnologyInventors: Fu'an He, Wenxu He, Bo Lin, Dehao Li, Zengtian Li, Wanyi Chen
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Patent number: D1024640Type: GrantFiled: November 17, 2020Date of Patent: April 30, 2024Assignees: King Slide Works Co., Ltd., King Slide Technology Co., Ltd.Inventors: Fang-Cheng Su, Ci-Bin Huang, Ching-Fu Chiu, Shu-Chen Lin