Abstract: A semiconductor device includes a first layer including a number of first layer metal pads, a second layer formed on top of the first layer, the second layer including a number of second layer metal pads, and vias connecting the first layer metal pads to the second layer metal pads. A surface area overlap between the first layer metal pads and the second layer metal pads is below a defined threshold.

Abstract: Embodiments of the disclosure provide an image sensor device. The image sensor device includes a semiconductor substrate. The semiconductor substrate has a front surface, a back surface opposite to the front surface, a light-sensing region close to the front surface, and a trench adjacent to the light-sensing region. The image sensor device includes a reflective layer positioned on an inner wall of the trench, wherein the reflective layer has a light reflectivity ranging from about 70% to about 100%.

Abstract: A backside illuminated (BSI) image sensor device includes: a first substrate including a front side and a back side; a second substrate bonded with the first substrate on the front side; and a blocking layer between the first substrate and the second substrate. The first substrate includes an image sensor, and the image sensor is configured to collect incident light entering from the back side. The second substrate includes a circuit coupled with the image sensor. The blocking layer is configured to block radiation induced by the circuit.

Abstract: A method of manufacturing a semiconductor device includes receiving a FinFET precursor including a fin structure formed between some isolation regions, and a gate structure formed over a portion of the fin structure; removing a top portion of the fin structure on either side of the gate structure; growing a semiconductive layer on top of a remaining portion of the fin structure such that a plurality of corners is formed over the fin structure; forming a capping layer over the semiconductive layer; performing an annealing process on the FinFET precursor to form a plurality of dislocations proximate to the corners; and removing the capping layer.

Abstract: A semiconductor device includes a gate structure on a substrate; a raised source/drain region adjacent to the gate structure; and an interconnect plug on the doped region. The raised source/drain region includes a top surface being elevated from a surface of the substrate; and a doped region exposed on the top surface. The doped region includes a dopant concentration greater than any other portions of the raised source/drain region. A bottommost portion of the interconnect plug includes a width approximate to a width of the doped region.

Abstract: A method of manufacturing a semiconductor structure includes providing a first wafer including a surface, removing some portions of the first wafer over the surface to form a plurality of recesses extended over at least a portion of the surface of the first wafer, providing a second wafer, and disposing the second wafer over the surface of the first wafer.

Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type region including a first conductivity type impurity. A first gate structure is on the semiconductor substrate overlying the first conductivity type region. A second conductivity type region including a second conductivity type impurity is formed in the semiconductor substrate. A barrier layer is located between the first conductivity type region and the second conductivity type region. The barrier layer prevents diffusion of the second conductivity type impurity from the second conductivity type region into the first conductivity type region.

Abstract: Some embodiments of the present disclosure provide a method of manufacturing a semiconductor device including receiving a FinFET precursor including a fin structure formed between isolation regions, and a gate structure formed over a portion of the fin structure such that a sidewall of the fin structure is in contact with a gate spacer of the gate structure; patterning the fin structure to comprise a pattern of at least one upward step rising from the isolation region; forming a capping layer over the fin structure, the isolation region, and the gate structure; performing an annealing process on the FinFET precursor to form at least two dislocations along the upward step; and removing the capping layer.

Abstract: A semiconductor structure includes a wafer including a first surface and a periphery, a plurality of protrusions protruded from the first surface and a plurality of recesses spaced from each other by the plurality of protrusions, and each of the plurality of recesses is extended from the periphery of the wafer and is elongated across the first surface of the wafer.

Abstract: Some embodiments of the present disclosure provide a method of manufacturing a semiconductor device including receiving a FinFET precursor including a fin structure formed between isolation regions, and a gate structure formed over a portion of the fin structure such that a sidewall of the fin structure is in contact with a gate spacer of the gate structure; patterning the fin structure to comprise a pattern of at least one upward step rising from the isolation region; forming a capping layer over the fin structure, the isolation region, and the gate structure; performing an annealing process on the FinFET precursor to form at least two dislocations along the upward step; and removing the capping layer.

Abstract: In a method for manufacturing a dual shallow trench isolation structure, a substrate is provided, and a mask layer is formed on the substrate. The mask layer is patterned by using a photomask to form at least one first hole and at least one second hole in the mask layer, in which a depth of the at least one first hole is different from a depth of the at least one second hole. The mask layer and the substrate are etched to form at least one first trench having a first depth and at least one second trench having a second depth, in which the first depth is different from the second depth. The remaining mask layer is removed. A first isolation layer and A second isolation layer are respectively formed in the at least one first trench and the at least one second trench.

Abstract: An integrated circuit structure includes a semiconductor substrate, an image sensor extending from a front surface of the semiconductor substrate into the semiconductor substrate, and an isolation structure extending from a back surface of the semiconductor substrate into the semiconductor substrate, wherein the isolation structure includes an air-gap therein. An air-gap sealing layer is on a backside of the semiconductor substrate. The air-gap sealing layer seals the air-gap, wherein the air-gap sealing layer includes a portion exposed to the air-gap.

Abstract: A backside illuminated (BSI) image sensor device includes: a first substrate including a front side and a back side; a second substrate bonded with the first substrate on the front side; and a blocking layer between the first substrate and the second substrate. The first substrate includes an image sensor, and the image sensor is configured to collect incident light entering from the back side. The second substrate includes a circuit coupled with the image sensor. The blocking layer is configured to block radiation induced by the circuit.

Abstract: A semiconductor device includes a first layer including a number of first layer metal pads, a second layer formed on top of the first layer, the second layer including a number of second layer metal pads, and vias connecting the first layer metal pads to the second layer metal pads. A surface area overlap between the first layer metal pads and the second layer metal pads is below a defined threshold.

Abstract: An integrated circuit structure includes a semiconductor substrate, an image sensor extending from a front surface of the semiconductor substrate into the semiconductor substrate, and an isolation structure extending from a back surface of the semiconductor substrate into the semiconductor substrate, wherein the isolation structure includes an air-gap therein. An air-gap sealing layer is on a backside of the semiconductor substrate. The air-gap sealing layer seals the air-gap, wherein the air-gap sealing layer includes a portion exposed to the air-gap.

Abstract: A backside illuminated (BSI) image sensor device includes a substrate including a front side and a back side; a radiation-sensing region in the substrate; a metal post with a longitudinal height and disposed over the back side; and a color filter adjacent to the metal post and substantially over the radiation-sensing region. The radiation-sensing region is configured to detect a radiation wave entering from the back side.

Abstract: Embodiments of the disclosure provide an image sensor device. The image sensor device includes a semiconductor substrate. The semiconductor substrate has a front surface, a back surface opposite to the front surface, a light-sensing region close to the front surface, and a trench adjacent to the light-sensing region. The image sensor device includes a reflective layer positioned on an inner wall of the trench, wherein the reflective layer has a light reflectivity ranging from about 70% to about 100%.

Abstract: A semiconductor structure includes a wafer including a first surface and a periphery, a plurality of protrusions protruded from the first surface and a plurality of recesses spaced from each other by the plurality of protrusions, and each of the plurality of recesses is extended from the periphery of the wafer and is elongated across the first surface of the wafer.

Abstract: A semiconductor device includes a first layer including a number of first layer metal pads, a second layer formed on top of the first layer, the second layer including a number of second layer metal pads, and vias connecting the first layer metal pads to the second layer metal pads. A surface area overlap between the first layer metal pads and the second layer metal pads is below a defined threshold.

Abstract: A semiconductor device includes a gate structure on a substrate; a raised source/drain region adjacent to the gate structure; and an interconnect plug on the doped region. The raised source/drain region includes a top surface being elevated from a surface of the substrate; and a doped region exposed on the top surface. The doped region includes a dopant concentration greater than any other portions of the raised source/drain region. A bottommost portion of the interconnect plug includes a width approximate to a width of the doped region.