Patents by Inventor Fu-Wei Chen

Fu-Wei Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190296121
    Abstract: In some embodiments, an integrated circuit is provided. The integrated circuit may include an inner ring-shaped isolation structure that is disposed in a semiconductor substrate. Further, the inner-ring shaped isolation structure may demarcate a device region. An inner ring-shaped well is disposed in the semiconductor substrate and surrounds the inner ring-shaped isolation structure. A plurality of dummy gates are arranged over the inner ring-shaped well. Moreover, the plurality of dummy gates are arranged within an interlayer dielectric layer.
    Type: Application
    Filed: June 11, 2019
    Publication date: September 26, 2019
    Inventors: Yi-Huan Chen, Chien-Chih Chou, Ta-Wei Lin, Fu-Jier Fan, Kong-Beng Thei, Yi-Sheng Chen, Szu-Hsien Liu
  • Patent number: 10340357
    Abstract: In some embodiments, an integrated circuit is provided. The integrated circuit may include an inner ring-shaped isolation structure that is disposed in a semiconductor substrate. Further, the inner-ring shaped isolation structure may demarcate a device region. An inner ring-shaped well is disposed in the semiconductor substrate and surrounds the inner ring-shaped isolation structure. A plurality of dummy gates are arranged over the inner ring-shaped well. Moreover, the plurality of dummy gates are arranged within an interlayer dielectric layer.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: July 2, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Huan Chen, Chien-Chih Chou, Ta-Wei Lin, Fu-Jier Fan, Kong-Beng Thei, Yi-Sheng Chen, Szu-Hsien Liu
  • Publication number: 20190164762
    Abstract: A method includes forming a gate stack and an interlayer dielectric (ILD) over a substrate, wherein the interlayer dielectric is adjacent to the gate stack; forming an inhibitor covering the interlayer dielectric such that the gate stack is exposed from the inhibitor; performing a deposition process to form a conductive layer over the gate stack until the conductive layer starts to form on the inhibitor, in which the deposition process has a deposition selectivity for the gate stack with respect to the inhibitor; and performing an etching process to remove a portion of the conductive layer over the inhibitor.
    Type: Application
    Filed: September 5, 2018
    Publication date: May 30, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Wei SU, Fu-Ting YEN, Ting-Ting CHEN, Teng-Chun TSAI
  • Publication number: 20190142180
    Abstract: An inflation identification connector and an air mattress system having the same is provided. The inflation identification connector is insertable into a connection seat of a gas delivery host. The connection seat has a light detection component coupled to a controller disposed in the gas delivery host. The inflation identification connector includes a body and an identification structure. The detection result of the light detection component depends on the identification structure and thus is conducive to identification. Upon its insertion into the connection seat, the inflation identification connector is identified by the gas delivery host, enhancing ease of use and protecting manual operation against mistakes. The gas delivery host is not only applicable to different types of air mattresses but also conducive to streamlined management of the air mattress system and reduction of management costs and risks.
    Type: Application
    Filed: October 30, 2018
    Publication date: May 16, 2019
    Inventors: DAVID HUANG, WEN-BIN SHEN, JU-CHIEN CHENG, MING-HENG HSIEH, FU-WEI CHEN, CHIH-KUANG CHANG, YI-LING LIU, SHENG-WEI LIN, CHUNG-YI LIN
  • Patent number: 9304167
    Abstract: An apparatus of three-dimensional integrated-circuit (3D-IC) chip is provided. The apparatus uses a test through-silicon-via (TSV). The test TSV is used as a redundant TSV operated under a normal mode. Vice versa, the test TSV is remained to be used as a traditional test TSV under a scan mode. The present invention significantly reduces the number of redundant TSVs and the production cost of the chip.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: April 5, 2016
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Ting-Ting Hwang, Fu-Wei Chen
  • Publication number: 20150185274
    Abstract: An apparatus of three-dimensional integrated-circuit (3D-IC) chip is provided. The apparatus uses a test through-silicon-via (TSV). The test TSV is used as a redundant TSV operated under a normal mode. Vice versa, the test TSV is remained to be used as a traditional test TSV under a scan mode. The present invention significantly reduces the number of redundant TSVs and the production cost of the chip.
    Type: Application
    Filed: March 14, 2014
    Publication date: July 2, 2015
    Applicant: National Tsing Hua University
    Inventors: Ting-Ting Hwang, Fu-Wei Chen
  • Publication number: 20120023549
    Abstract: A method for inviting a challenged entity to provide input concerning a sinograph includes displaying, to the challenged entity, a first region having an image of a challenge sinograph; displaying at least a first event-sensitive region, the first event-sensitive region having an image of a real root of the challenge sinograph; and displaying at least a second event-sensitive region. The second event sensitive region has an image of a faux root of the challenge sinograph.
    Type: Application
    Filed: July 21, 2011
    Publication date: January 26, 2012
    Applicant: Academia Sinica
    Inventors: Ling-Jyh Chen, Der-Ming Juang, Wen-Yuan Zhu, Hsiao-Hsuan Yu, Fu-Wei Chen
  • Patent number: 7633905
    Abstract: Calibrating a transmit diversity device includes establishing diversity parameter values of diversity parameters for a plurality of signals, where each signal is transmitted from a channel of the transmit diversity device. The following are performed for each diversity parameter value to yield associations: determining a modification parameter value that yields a diversity parameter value, where a modification parameter value describes modulation of a feature of at least one signal; and associating the modification parameter value with the diversity parameter value to yield an association. Calibration data is generated in accordance with the associations.
    Type: Grant
    Filed: November 18, 2005
    Date of Patent: December 15, 2009
    Assignee: Magnolia Broadband Inc.
    Inventors: Haim Harel, Yair Karmi, Phil Fu-Wei Chen, Kenneth A. Kludt
  • Patent number: 7630445
    Abstract: Establishing slot boundaries includes receiving a feedback signal reflecting feedback information describing a signal modified according to a diversity parameter adjustment. The feedback signal includes slots and bits. A slot boundary is established for each of the slots by: partitioning the bits into periods; comparing the bits of each period; and establishing the slot boundaries in accordance with the comparison.
    Type: Grant
    Filed: October 25, 2005
    Date of Patent: December 8, 2009
    Assignee: Magnolia Broadband Inc.
    Inventors: Yair Karmi, Phil Fu-Wei Chen
  • Patent number: 6611756
    Abstract: A method for enhancing data wipeoff by predicting future navigation data. Data wipeoff using predicted future navigation data reduces or eliminates incomplete data wipeoff, thereby enhancing GPS receiver sensitivity and reducing acquisition times. Predicting future navigation data involves receiving navigation data and using the received navigation data to generate predicted future navigation data, wherein the predicted future navigation data should be approximately identical to navigation data received at a future time. The predicted future navigation data is subsequently used to perform data wipeoff.
    Type: Grant
    Filed: August 10, 2000
    Date of Patent: August 26, 2003
    Assignee: Lucent Technologies Inc.
    Inventors: Phil Fu-Wei Chen, Andrew Todd Zidel