Abstract: One embodiment of the present disclosure provides a semiconductor package including a bottom chip package having a first side and a second side opposing the first side, and a top antenna package mounted on the first side of the bottom chip package. The bottom chip package further includes a semiconductor chip. The semiconductor chip may include a RFIC chip. The top antenna package has at least one radiative antenna element.

Abstract: One embodiment of the present disclosure provides a semiconductor package including a bottom chip package having a first side and a second side opposing the first side, and a top antenna package mounted on the first side of the bottom chip package. The bottom chip package further includes a semiconductor chip. The semiconductor chip may include a RFIC chip. The top antenna package has at least one radiative antenna element.

Abstract: One embodiment of the present disclosure provides a semiconductor package including a bottom chip package having a first side and a second side opposing the first side, and a top antenna package mounted on the first side of the bottom chip package. The bottom chip package further includes a semiconductor chip. The semiconductor chip may include a RFIC chip. The top antenna package has at least one radiative antenna element.

Abstract: One embodiment of the present disclosure provides a semiconductor package including a bottom chip package having a first side and a second side opposing the first side, and a top antenna package mounted on the first side of the bottom chip package. The bottom chip package further includes a semiconductor chip. The semiconductor chip may include a RFIC chip. The top antenna package has at least one radiative antenna element.

Abstract: A power management device includes a first power unit, a second power unit, and a control unit. The first power unit receives a first control signal of a first phase to generate a first current of the first phase flowing to an output node. The second power unit receives a second control signal of a second phase to generate a second current of the second phase flowing to the output node. A phase delay is the difference between the first phase and the second phase. The control unit receives a clock signal in a clock frequency to generate the first control signal and the second control signal. The control unit controls the phase delay to cancel a corresponding harmonic of the clock frequency at the output node.

Abstract: A power management device includes a first power unit, a second power unit, and a control unit. The first power unit receives a first control signal of a first phase to generate a first current of the first phase flowing to an output node. The second power unit receives a second control signal of a second phase to generate a second current of the second phase flowing to the output node. A phase delay is the difference between the first phase and the second phase. The control unit receives a clock signal in a clock frequency to generate the first control signal and the second control signal. The control unit controls the phase delay to cancel a corresponding harmonic of the clock frequency at the output node.

Abstract: An active 90-degree phase shifter with LC-type emitter (source) degeneration is provided, which is practiced in an integrated circuit. The phase shifter comprises a first differential amplifier, having one first signal output end and comprising an inductor, a first transistor and a second transistor, wherein the inductor is connected to the emitters (sources) of the first and the second transistors; and a second differential amplifier, having one second signal output end and comprising a capacitor, a third transistor and a fourth transistor, wherein the capacitor is connected to the emitters (sources) of the third and the fourth transistors. Wherein the bases (gates) of the first and the fourth transistors are signal input ends, and the bases (gates) of the second and the third transistors are coupled together.

Abstract: An active 90-degree phase shifter with LC-type emitter (source) degeneration is provided, which is practiced in an integrated circuit. The phase shifter comprises a first differential amplifier, having one first signal output end and comprising an inductor, a first transistor and a second transistor, wherein the inductor is connected to the emitters (sources) of the first and the second transistors; and a second differential amplifier, having one second signal output end and comprising a capacitor, a third transistor and a fourth transistor, wherein the capacitor is connected to the emitters (sources) of the third and the fourth transistors. Wherein the bases (gates) of the first and the fourth transistors are signal input ends, and the bases (gates) of the second and the third transistors are coupled together.