Abstract: A trench PT IGBT (or NPT IGBT) having clamp diodes for ESD protection and prevention of shortage among gate, emitter and collector. The clamp diodes comprise multiple back-to-back Zener Diode composed of doped regions in a polysilicon layer doped with dopant ions of a first conductivity type next to a second conductivity type disposed on an insulation layer above said semiconductor power device. Trench gates are formed underneath the contact areas of the clamp diodes as the buffer layer for prevention of shortage.

Abstract: A trench MOSFET with copper metal connections includes a substrate provided with a plurality of trenches. A gate oxide layer is formed on the sidewalls and bottoms of the trenches. A conductive layer is filled in the trenches to be used as a gate of the MOSFET. A plurality of source and body regions are formed in an epi layer. An insulating layer is formed on the epi layer and formed with a plurality of metal contact holes therein for contacting respective source and body regions. A barrier metal layer is formed on the sidewalls and bottoms of the metal contact holes in direct contact with respective source and body regions. A metal contact layer is filled in the metal contact holes. A copper metal layer is formed on another barrier metal layer on the insulating layer connected to respective source regions through the metal contact layer to form metal connections of the MOSFET.

Abstract: A trench MOSFET with on-resistance reduction comprises a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate, wherein the said MOSFET further comprises a plurality of source-body contact trenches opened relative to a top surface into said source and body regions and each of the source-body contact trenches is filled with a contact metal plug as a source-body contact; a insulation layer covered over the top of the trenched gate, the body region and the source region; a front metal layer formed on a top surface of the MOSFET; wherein a low-resistivity phosphorus substrate and retrograded P-body formed by medium or high energy Ion Implantation to reduce Rds contribution from substrate and drift region.

Abstract: A trench MOSFET structure having improved avalanche capability is disclosed, wherein the source region is formed by performing source Ion Implantation through contact open region of a contact interlayer, and further diffused to optimize a trade-off between Rds and the avalanche capability. Thus, only three masks are needed in fabrication process, which are trench mask, contact mask and metal mask. Furthermore, said source region has a doping concentration along channel region lower than along contact trench region, and source junction depth along channel region shallower than along contact trench, and source doping profile along surface of epitaxial layer has Guassian-distribution from trenched source-body contact to channel region.

Abstract: A method of forming trench MOSFET structure having improved avalanche capability is disclosed. In a preferred embodiment according to the present invention, only three masks are needed in the fabricating process, wherein the source region is formed by performing source Ion Implantation through contact open region of a thick contact interlayer for saving source mask. Furthermore, said source region has a doping concentration along channel region lower than along contact trench region, and source junction depth along channel region shallower than along contact trench, and source doping profile along surface of epitaxial layer has Guassian-distribution from trenched source-body contact to channel region.

Abstract: A structure of power semiconductor device integrated with clamp diodes sharing same gate metal pad is disclosed. This improved structure can prevent the degradation of breakdown voltage due to electric field in termination region blocked by polysilicon.

Abstract: A trench MOSFET with trench source contact structure having copper wire bonding is disclosed. By employing the proposed structure, die size can be shrunk into 30%˜70% with high cell density, and the spreading resistance is significantly reduce without adding expensive thick metal layer as prior art. To further reduce fabricating cost, copper wire bonding is used with requirement of thick Al alloys.

Abstract: A semiconductor power device with Zener diode for providing an electrostatic discharge (ESD) protection and a thick insulation layer to insulate the Zener diode from a doped body region. The semiconductor power device further includes a Nitride layer underneath the thick oxide layer working as a stopper layer for protecting the thin oxide layer and the body region underneath whereby the over-etch damage and punch-through issues in process steps are eliminated.

Abstract: A structure of power semiconductor device integrated with clamp diodes having separated gate metal pad is disclosed. The separated gate metal pads are wire bonded together on the gate lead frame. This improved structure can prevent the degradation of breakdown voltage due to electric field in termination region blocked by polysilicon.

Abstract: A structure of power semiconductor device having dummy cells around edge of active area is disclosed. The UIS test result of said improved structure shows that failed site after UIS test randomly located in active area which means avalanche capability of the semiconductor power device is enhanced by implementation of the dummy cells.

Abstract: An integrated configuration comprising trench MOSFET having trench contacts and trench Schottky rectifier having planar contacts is disclosed. The trench contacts for trench MOSFET provide a lower specific on-resistance. Besides, for trench gate connection, planar gate contact is employed in the present invention to avoid shortage issue between gate and drain in shallow trench gate. Besides, W plugs filled into both trench contacts and planar contacts enhance the metal step coverage capability.

Abstract: An integrated circuit includes a plurality of trench MOSFET and a plurality of trench Schottky rectifier. The integrated circuit further comprises: tilt-angle implanted body dopant regions surrounding a lower portion of all trench gates sidewalls for reducing Qgd; a source dopant region disposed below a bottom surface of all trench gates for functioning as a current path for preventing a resistance increased caused by the body dopant regions.

Abstract: A trench MOSFET structure having improved avalanche capability is disclosed, wherein the source region is formed by performing source Ion Implantation through contact open region of a thick contact interlayer, and further diffused to optimize a trade-off between Rds and the avalanche capability. Thus, only three masks are needed in fabrication process, which are trench mask, contact mask and metal mask. Furthermore, said source region has a doping concentration along channel region lower than along contact trench region, and source junction depth along channel region shallower than along contact trench, and source doping profile along surface of epitaxial layer has Gaussian-distribution from trenched source-body contact to channel region.

Abstract: A trench MOSFET in parallel with trench Schottky barrier rectifier is formed on a single substrate. The present invention solves the constrains brought by planar contact of Schottky, for example, the large area occupied by planar structure. As the size of present device is getting smaller and smaller, the trench Schottky structure of this invention is able to be shrink and, at the same time, to achieve low specific on-resistance. By applying a double epitaxial layer in trench Schottky barrier rectifier, the device performance is enhanced for lower Vf and lower reverse leakage current Ir is achieved.

Abstract: A trench Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) structure with guard ling, includes: a substrate including an epi layer region on the top thereof a plurality of source and body regions formed in the epi layer; a metal layer including a plurality of metal layer regions which are connected to respective source and body regions forming metal connections of the MOSFET; a plurality of metal contact plugs connected to respective metal layer regions; an insulating layer deposited on the epi layer formed underneath the metal layer with a plurality of metal contact holes therein for contacting respective source and body regions; and a guard ring wrapping around the trench gates with contact metal plug underneath the gate metal layer.

Abstract: A LDMOS with double LDD and trenched drain is disclosed. According to some preferred embodiment of the present invention, the structure contains a double LDD region, including a high energy implantation to form lightly doped region and a low energy implantation thereon to provide a low resistance path for current flow without degrading breakdown voltage. At the same time, a P+ junction made by source mask is provided underneath source region to avoid latch-up effect from happening.

Abstract: A trench MOSFET device with embedded Schottky rectifier, gate-drain and gate-source diodes on single chip is formed with shallow trench structure to achieve device shrinkage and performance improvement. The present semiconductor devices achieve low Vf and reverse leakage current for embedded Schottky rectifier, have overvoltage protection for GS clamp diodes and avalanche protection for GD clamp diodes.

Abstract: A trench DMOS transistor employing trench contacts has overvoltage protection for prevention of shortage between gate and source, comprising a plurality of first-type function trenched gates, at least one second-type function trenched gate and at least two third-type function trenched gates extending through body regions and into an epitaxial layer. The first-type function trenched gates are located in active area surrounded by a source region encompassed in the body region in the epitaxial layer for current conduction. The second-type function trenched gates are disposed underneath a gate metal with a gate trenched contacts filled with metal plug for gate metal connection. The third type function trenched gates are disposed directly and symmetrically underneath ESD trenched contact areas of anode and cathode in an ESD protection diode, serving as a buffer layer for prevention of gate-body shortage.

Abstract: An integrated configuration comprising trench MOSFET having trench contacts and trench Schottky rectifier having planar contacts is disclosed. The trench contacts for trench MOSFET provide a lower specific on-resistance. Besides, for trench gate connection, planar gate contact is employed in the present invention to avoid shortage issue between gate and drain in shallow trench gate. Besides, W plugs filled into both trench contacts and planar contacts enhance the metal step coverage capability.

Abstract: A trench MOSFET with improved metal schemes is disclosed. The improved contact structure applies a buffer layer to minimize the bonding damage to semiconductor when bonding copper wire upon front source and gate metal without additional cost.