Abstract: A Schottky diode includes an insulating substrate and at least one Schottky diode unit. The at least one Schottky diode unit is located on a surface of the insulating substrate. The at least one Schottky diode unit includes a first electrode, a semiconductor structure and a second electrode. The semiconductor structure comprising a first end and a second end. The first end is laid on the first electrode, the second end is located on the surface of the insulating substrate. The semiconducting structure includes a carbon nanotube structure. The second electrode is located on the second end.

Abstract: A Schottky diode includes a first electrode, a second electrode and a semiconducting structure. The first electrode includes a first metal layer and a second metal layer. The second electrode includes a third metal layer and a fourth metal layer. The semiconductor structure includes a first end and a second end. The first end is sandwiched by the first metal layer and the second metal layer, the second end is sandwiched by the third metal layer and the fourth metal layer. The semiconductor structure is a nano-scale semiconductor structure.

Abstract: A Schottky diode includes a first electrode, a second electrode and a semiconducting structure. The first electrode includes a first metal layer and a second metal layer. The second electrode includes a third metal layer and a fourth metal layer. The semiconductor structure includes a first end and a second end. The first end is sandwiched by the first metal layer and the second metal layer, the second end is sandwiched by the third metal layer and the fourth metal layer. The semiconductor structure includes a carbon nanotube structure.

Abstract: A Schottky diode includes an insulating substrate and at least one Schottky diode unit. The at least one Schottky diode unit is located on a surface of the insulating substrate. The at least one Schottky diode unit includes a first electrode, a semiconductor structure and a second electrode. The semiconductor structure comprising a first end and a second end. The first end is laid on the first electrode, the second end is located on the surface of the insulating substrate. The semiconducting structure is nano-scale semiconductor structure. The second electrode is located on the second end.

Abstract: A system for monitoring impedance of excitable cells in vitro, which includes a device for monitoring cell-substrate impedance at 20 millisecond resolution, which includes a nonconductive substrate with one or more electrode arrays fabricated in one or more wells, wherein cell attachment on the substrate can result in a detectable change in impedance between electrodes within each electrode array; an impedance analyzer capable of impedance measurement at 20 millisecond time resolution; electronic circuitry that can engage said device and selectively connect said two or more electrode arrays of said device to said impedance analyzer; and a software program that controls said electronic circuitry and records and analyzes data obtained from said impedance analyzer.

Abstract: An in-situ testing equipment for testing micromechanical properties of a material in a multi-load and multi-physical field coupled condition is disclosed. The equipment comprises a frame supporting module, a tension/compression-low cycle fatigue module, a torsioning module (21), a three-point bending module (6), an impressing module (33), a thermal field and magnetic field application module (34), an in-situ observation module (32) and a clamp body module (22).

Abstract: The disclosure relates to a thin film transistor and a method for making the same. The thin film transistor includes a substrate; a semiconductor layer on the substrate, wherein the semiconductor layer includes nano-scaled semiconductor materials; a source and a drain, wherein the source and the drain are on the substrate, spaced apart from each other, and electrically connected to the semiconductor layer; a dielectric layer on the semiconductor layer, wherein the dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer stacked on one another, and the first sub-dielectric layer is a first oxide dielectric layer grown by magnetron sputtering; and a gate in direct contact with the first sub-dielectric layer. The thin film transistor almost has no current hysteresis.

Abstract: The disclosure relates to a thin film transistor and a method for making the same. The thin film transistor includes a substrate; a gate located on the substrate; a dielectric layer located on the gate; a semiconductor layer located on the dielectric layer and including nano-scaled semiconductor materials; and a drain and a source spaced apart from each other and electrically connected to the semiconductor layer. The dielectric layer is an oxide layer formed by magnetron sputtering and in direct contact with the gate. The thin film transistor has inverse current hysteresis.

Abstract: The disclosure relates to a logic circuit. The logic circuit includes a n-type thin film transistor and a p-type thin film transistor. Each thin film transistor includes a substrate; a semiconductor layer including nano-scaled semiconductor materials; a source and a drain, wherein the source and the drain are spaced apart from each other, and electrically connected to the semiconductor layer; a dielectric layer covering the semiconductor layer, wherein the dielectric layer includes a normal dielectric layer and an abnormal dielectric layer stacked on one another, and the abnormal dielectric layer is an oxide dielectric layer grown by magnetron sputtering; and a gate in direct contact with the abnormal dielectric layer. The n-type thin film transistor and the p-type thin film transistor share the same substrate and the same gate.

Abstract: The disclosure relates to a thin film transistor and a method for making the same. The thin film transistor includes a substrate; a gate on the substrate; a dielectric layer on the gate, wherein the dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer stacked on one another, and the first sub-dielectric layer is a first oxide dielectric layer formed by magnetron sputtering and in direct contact with the gate; a semiconductor layer on the dielectric layer, wherein the semiconductor layer includes nano-scaled semiconductor materials; and a source and a drain, wherein the source and the drain are on the dielectric layer, spaced apart from each other, and electrically connected to the semiconductor layer. The thin film transistor almost has no current hysteresis.

Abstract: The disclosure relates to a logic circuit. The logic circuit includes two ambipolar thin film transistors. Each of the two ambipolar thin film transistors includes a substrate; a semiconductor layer located on the substrate and including nano-scaled semiconductor materials; a source and a drain, wherein the source and the drain are located on the substrate, spaced apart from each other, and electrically connected to the semiconductor layer; a dielectric layer located on the substrate and covering the semiconductor layer, wherein the dielectric layer includes a normal dielectric layer and an abnormal dielectric layer stacked on one another, and the abnormal dielectric layer is an oxide dielectric layer grown by magnetron sputtering; and a gate in direct contact with the abnormal dielectric layer. The two ambipolar thin film transistors share the same substrate, the same gate, and the same drain.

Abstract: The disclosure relates to a thin film transistor and a method for making the same. The thin film transistor includes a substrate; a semiconductor layer on the substrate, wherein the semiconductor layer includes nano-scaled semiconductor materials; a source and a drain, wherein the source and the drain are on the substrate, spaced apart from each other, and electrically connected to the semiconductor layer; a dielectric layer on the semiconductor layer, wherein the dielectric layer is an oxide dielectric layer formed by magnetron sputtering; and a gate in direct contact with the dielectric layer. The thin film transistor has inverse current hysteresis.

Abstract: A system for monitoring impedance of excitable cells in vitro, which includes a device for monitoring cell-substrate impedance at 20 millisecond resolution, which includes a nonconductive substrate with one or more electrode arrays fabricated in one or more wells, wherein cell attachment on the substrate can result in a detectable change in impedance between electrodes within each electrode array; an impedance analyzer capable of impedance measurement at 20 millisecond time resolution; electronic circuitry that can engage said device and selectively connect said two or more electrode arrays of said device to said impedance analyzer; and a software program that controls said electronic circuitry and records and analyzes data obtained from said impedance analyzer.

Abstract: A device may receive information identifying a model including information associated with elements included in the model. The device may cause the model to be executed, and may collect data associated with executing the model. The device may determine performance information based on the collected data. The performance information may be associated with the elements included in the model. The device may generate a heat map based on the performance information. The heat map may associate an element, of the elements, with a visual representation indicating performance information, associated with the element, based on a heat map scale. The heat map scale may relate the performance information, associated with the element, to performance information associated with another element. The heat map may be a graphical interface that includes a graphical representation of the element and a graphical representation of the other element. The device may provide the heat map.

Abstract: A method of determining a beating parameter of cells that undergo excitation contraction coupling, the method including providing a cell analysis device having a substrate and a sensor that measures cell adhesion or attachment to the substrate in millisecond time resolution; adding excitable cells capable of undergoing excitation contraction coupling to the substrate; monitoring cell adhesion or attachment of the excitable cells to the substrate in millisecond time resolution; and calculating one or more beating parameters from the monitored adhesion.

Abstract: Systems and methods for improved monitoring of excitation-contraction coupling and excitable cells are provided, which provide millisecond time resolution. The system is capable of continuously monitoring excitation-contraction coupling in a relatively high-throughput manner. The system includes a device for monitoring cell-substrate impedance, an impedance analyzer capable of impedance measurements at millisecond time resolution, electronic circuitry that can engage the device and selectively connect two or more electrode arrays of the device to the impedance analyzer and a software program that controls the electronic circuitry and records and analyzes data obtained from the impedance analyzer.

Abstract: A method of determining one or more beating parameters for use in cardiomyocyte beating analysis including: providing a cell analysis device including wells, each well including a sensor capable of monitoring beating of cardiomyoctes in millisecond time resolution; adding cardiomyocytes to the wells; monitoring the beating of the cardiomyocytes in millisecond time resolution to obtain a plurality of beating measurements; and calculating one or more beating parameters from the plurality of beating measurements.

Abstract: A method may include causing a first model to be executed. The causing the first model to be executed may be performed by a device. The method may further include causing a second model to be executed to simulate a functionality of the first model. The causing the second model to be executed may be performed by the device. The method may further include interacting with a model element, of the second model, associated with implicitly accessing information regarding a state of the first model. The state may be a representation of the first model at a particular simulation time-step. The interacting with the model may be performed by the device. The method may further include accessing, by the model element, information associated with the state of the first model. The accessing the information may be performed by the device.

Abstract: An in-situ testing equipment for testing micromechanical properties of a material in a multi-load and multi-physical field coupled condition is disclosed. The equipment comprises a frame supporting module, a tension/compression-low cycle fatigue module, a torsioning module (21), a three-point bending module (6), an impressing module (33), a thermal field and magnetic field application module (34), an in-situ observation module (32) and a clamp body module (22).

Abstract: A method, performed by a computer device, may include selecting one or more input and output points in an executable graphical model in a modeling application and simulating the executable graphical model over a plurality of time points. The method may further include generating a time domain response plot for the executable graphical model based on the simulating; obtaining matrices of partial derivatives based on the selected one or more input and output points at particular time points of the plurality of time points; generating a frequency domain response plot for the executable graphical model based on the obtained matrices of partial derivatives; and generating a bidomain simulator user interface, the bidomain simulator user interface including the generated time domain response plot and the generated frequency domain response plot.