Patents by Inventor Fuat Keceli

Fuat Keceli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11372464
    Abstract: An apparatus is provided which comprises: a controller to allocate, to a component, a resource budget selected from a plurality of quantization levels; and a circuitry to adaptively update the plurality of quantization levels.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: June 28, 2022
    Assignee: Intel Corporation
    Inventors: Fuat Keceli, Frederico Ardanaz, Jonathan M. Eastep, Ankush Varma, Krishnakanth V. Sistla
  • Patent number: 11061460
    Abstract: Embodiments of the present disclosure describe methods, apparatuses, storage media, and systems for Thermal Design Power (TDP) rebalancing among thermally-coupled processors and non-thermally-coupled processors, providing computing efficiency or homogeneity with respect to, including but not limited to, thermal requirements, power consumption, and processor operations. The TDP rebalancing may include implementing management circuitry and configuration control circuitry. Other embodiments may be described and claimed.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: July 13, 2021
    Assignee: Intel Corporation
    Inventors: Fuat Keceli, Tozer J. Bandorawalla, Grant McFarland, Jonathan M. Eastep, Federico Ardanaz
  • Publication number: 20210191490
    Abstract: Methods and apparatus for balancing power between discrete components, such as processing units (e.g., CPUs) and accelerators in a compute node or platform. Power consumption of the compute platform is monitored to detect for conditions under which a threshold (e.g., power supply capacity threshold) is exceeded. In response, the operating frequencies of a processing unit and/or other platform components such as accelerators, are adjusted to reduce the power consumption of the platform to return below the threshold. Power limit biasing hints (scaling weights) are provided to platform components, along with a power violation index, which are used to adjust the operating frequencies of the platform components. Optionally, a processing unit can calculate the power violation index and the scaling weights and directly control the frequencies of itself and platform components. Embodiments of multi-socket platforms are also provided.
    Type: Application
    Filed: March 3, 2021
    Publication date: June 24, 2021
    Inventors: Phani Kumar KANDULA, Eric J. DEHAEMER, Dorit SHAPIRA, Ramkumar NAGAPPAN, Vivek GARG, Fuat KECELI, Mani PRAKASH, David C. HOLCOMB, Horthense D. TAMDEM, Olivier FRANZA, Vjekoslav SVILAN
  • Patent number: 10908668
    Abstract: Systems, apparatuses and methods may provide for determining, from a program comprising graphs of parallel operations and dependencies, an estimation of a droop risk associated with execution of the graphs by a load. A risk signal may be outputted based on the estimation. The risk signal may be associated with an adjustment in an output voltage of a voltage regulator and the output voltage is to be provided to the load.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: February 2, 2021
    Assignee: Intel Corporation
    Inventors: Fuat Keceli, Jonathan Eastep, Kelly Livingston, Federico Ardanaz
  • Patent number: 10684663
    Abstract: Systems, apparatuses and methods may provide for receiving indicator data associated with activity of a load. Additionally, an estimation of a rate of change of a current of the load with respect to time may be determined from the indicator data. Moreover, a boost signal may be selectively output to a voltage regulator when the estimation of the rate of change is greater than a first amount. The boost signal may be associated with an adjustment in an output voltage of the voltage regulator and the output voltage may be provided to the load.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Kelly Livingston, Federico Ardanaz, Dmitry Lukianchenko, Fuat Keceli, Jonathan Eastep
  • Publication number: 20190324517
    Abstract: Embodiments of the present disclosure describe methods, apparatuses, storage media, and systems for Thermal Design Power (TDP) rebalancing among thermally-coupled processors and non-thermally-coupled processors, providing computing efficiency or homogeneity with respect to, including but not limited to, thermal requirements, power consumption, and processor operations. The TDP rebalancing may include implementing management circuitry and configuration control circuitry. Other embodiments may be described and claimed.
    Type: Application
    Filed: June 28, 2019
    Publication date: October 24, 2019
    Inventors: Fuat Keceli, Tozer J. Bandorawalla, Grant McFarland, Jonathan M. Eastep, Federico Ardanaz
  • Publication number: 20190041942
    Abstract: Systems, apparatuses and methods may provide for determining, from a program comprising graphs of parallel operations and dependencies, an estimation of a droop risk associated with execution of the graphs by a load. A risk signal may be outputted based on the estimation. The risk signal may be associated with an adjustment in an output voltage of a voltage regulator and the output voltage is to be provided to the load.
    Type: Application
    Filed: December 29, 2017
    Publication date: February 7, 2019
    Inventors: Fuat Keceli, Jonathan Eastep, Kelly Livingston, Federico Ardanaz
  • Publication number: 20190041930
    Abstract: Systems, apparatuses and methods may provide for receiving indicator data associated with activity of a load. Additionally, an estimation of a rate of change of a current of the load with respect to time may be determined from the indicator data. Moreover, a boost signal may be selectively output to a voltage regulator when the estimation of the rate of change is greater than a first amount. The boost signal may be associated with an adjustment in an output voltage of the voltage regulator and the output voltage may be provided to the load.
    Type: Application
    Filed: December 28, 2017
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: Kelly Livingston, Federico Ardanaz, Dmitry Lukianchenko, Fuat Keceli, Jonathan Eastep
  • Publication number: 20180356868
    Abstract: An apparatus is provided which comprises: a controller to allocate, to a component, a resource budget selected from a plurality of quantization levels; and a circuitry to adaptively update the plurality of quantization levels.
    Type: Application
    Filed: September 28, 2017
    Publication date: December 13, 2018
    Inventors: Fuat Keceli, Federico Ardanaz, Jonathan M. Eastep, Ankush Varma, Krishnakanth V. Sistla