Abstract: An electrically erasable programmable read only memory (EEPROM) emulation (EEE) system includes a non-volatile memory arranged to have a plurality of sectors in which each sector is arranged to have a plurality of record locations. A new record of new data is programmed into a record location of an active sector of the plurality of sectors. After successfully completing the programming of the new record, a number of failure-to-program (FTP) occurrences during the programming is compared to a first threshold. When the number of FTP occurrences is greater than the first threshold, a determination is made as to whether compression is needed, and in response to determining that compression is needed, the method includes selectively performing compression based on a second threshold.

Abstract: An electrically erasable programmable read only memory (EEPROM) emulation (EEE) system includes a non-volatile memory arranged to have a plurality of sectors in which each sector is arranged to have a plurality of record locations. A new record of new data is programmed into a record location of an active sector of the plurality of sectors. After successfully completing the programming of the new record, a number of failure-to-program (FTP) occurrences during the programming is compared to a first threshold. When the number of FTP occurrences is greater than the first threshold, a determination is made as to whether compression is needed, and in response to determining that compression is needed, the method includes selectively performing compression based on a second threshold.

Abstract: A method and memory for stressing a plurality of non-volatile memory cells is provided. The method includes entering a memory cell stressing mode and providing one or more erase stress pulses to the plurality of non-volatile memory cells; determining that a threshold voltage of at least a subset of the plurality of non-volatile memory cells has a first relationship that is either greater than or less than a first predetermined voltage; providing one or more program stress pulses to the plurality of memory cells; and determining that the threshold voltage of at least a subset of the plurality of memory cells has a second relationship to a second predetermined voltage that is different than the first relationship.

Abstract: A non-volatile memory is arranged to have a plurality of sectors. Each sector of the plurality of sectors includes a plurality of record locations. A memory controller includes an erase counter, a failed sector flag, and a retired sector flag for each of the plurality of sectors. If a record location of a sector fails to program, another location in the sector is selected to be programmed. The failed sector flag is set if a predetermined number of selected record locations of the sector fails to program. If the failed sector flag is set for a particular sector twice, and an erase count is greater than a predetermined erase count, then the retired sector flag is set for the failed sector indicating the sector is to be permanently retired from use. A new sector of the plurality of sectors becomes the current active sector for record programming operations. The method for retiring a sector occurs dynamically, during operation of the non-volatile memory.

Abstract: A method and memory for stressing a plurality of non-volatile memory cells is provided. The method includes entering a memory cell stressing mode and providing one or more erase stress pulses to the plurality of non-volatile memory cells; determining that a threshold voltage of at least a subset of the plurality of non-volatile memory cells has a first relationship that is either greater than or less than a first predetermined voltage; providing one or more program stress pulses to the plurality of memory cells; and determining that the threshold voltage of at least a subset of the plurality of memory cells has a second relationship to a second predetermined voltage that is different than the first relationship.

Abstract: Methods and systems are disclosed for extended erase protection for non-volatile memory (NVM) cells during embedded erase operations for NVM systems. The embodiments described herein utilize an additional threshold voltage (Vt) check after soft programming operation within an embedded erase operation completes to provide extended erase protection of NVM cells. In particular, the threshold voltages for NVM cells are compared against a threshold voltage (Vt) check voltage (VCHK) level and an additional embedded erase cycle is performed if any NVM cells are found to exceed the threshold voltage (Vt) check voltage (VCHK) level. The threshold voltage (Vt) check voltage (VCHK) level can be, for example, a voltage level that is slightly higher than an erase verify voltage (VEV) level and lower than read voltage level (VR).

Abstract: A method of soft programming a non-volatile memory (NVM) array includes determining a first number based on a temperature of the NVM array and applying the first number of soft program pulses to a section of the NVM array. A first soft program verify of the section of the NVM array is then performed for a first time after completing the applying the first number of soft program pulses.

Abstract: A method of programming a non-volatile semiconductor memory device includes determining a number of bit cells that failed to program verify during a program operation. The bit cells are included in a subset of bit cells in an array of bit cells. The method further determines whether an Error Correction Code (ECC) correction has been previously performed for the subset of bit cells. The program operation is considered successful if the number of bit cells that failed to program verify after a predetermined number of program pulses is below a threshold number and the ECC correction has not been performed for the subset of bit cells.

Abstract: Methods and systems are disclosed for adjusting read/verify bias conditions for non-volatile memory (NVM) cells to improve performance and product lifetime of NVM systems. System embodiments include integrated NVM systems having a NVM controller, a bias voltage generator, and an NVM cell array. Further, the NVM systems can store performance degradation information and read/verify bias condition information within storage circuitry. The disclosed embodiments adjust read/verify bias conditions for the NVM cells based upon performance degradation determinations, for example, temperature-based performance degradation determinations.

Abstract: A method includes an erase of a plurality of blocks of memory cells in which the memory cells within a block are simultaneously erased. The erase of each block of the plurality of blocks is performed using an erase pulse applied multiple times. The erase pulse is applied to the plurality of blocks in parallel. An erase verify is performed after each application of the erase pulse. After a number applications of the erase pulse, it is determined if a condition comprising one of a group consisting of any memory cell has been more erased than a first predetermined amount and any memory cell has been erased less than a second predetermined amount has been met. If the condition has been met, erasing is continued by applying the erase pulse to the block having the memory cell with the condition independently of the other blocks of the plurality of blocks.

Abstract: In accordance with at least one embodiment, a method and apparatus for improving the ability to correct errors in memory devices is described. At least one embodiment provides a way to salvage the part even it has double-bit or multi-bit error from the same ECC section, thus improving product reliability and extending the product lifetime. During a normal read, if a double-bit or multiple-bit error happens, which ECC can detect but cannot fix, the error is corrected by adjusting the read voltage level and reading again to determine the proper read level (and, therefore, the correct value being read). This dynamic read scheme can apply to extrinsic bits from either erase state or program state. It can be also used in a single bit scenario to minimize ECC occurrence and save ECC capacity.

Abstract: Methods and systems are disclosed for adaptive erase recovery of non-volatile memory (NVM) cells within NVM systems. The adaptive erase recovery embodiments adaptively adjust the erase recovery discharge rate and/or discharge time based upon the size of NVM block(s) being erased and operating temperature. In one example embodiment, the erase recovery discharge rate is adjusted by adjusting the number of discharge transistors enabled within the discharge circuitry, thereby adjusting the discharge current for erase recovery. A lookup table is used to store erase recovery discharge rates and/or discharge times associated with NVM block sizes to be recovered and/or operating temperature. By adaptively controlling erase recovery discharge rates and/or times, the disclosed embodiments improve overall erase performance for a wide range of NVM block sizes while avoiding possible damage to high voltage circuitry within the NVM system.

Abstract: A method includes an erase of a plurality of blocks of memory cells in which the memory cells within a block are simultaneously erased. The erase of each block of the plurality of blocks is performed using an erase pulse applied multiple times. The erase pulse is applied to the plurality of blocks in parallel. An erase verify is performed after each application of the erase pulse. After a number applications of the erase pulse, it is determined if a condition comprising one of a group consisting of any memory cell has been more erased than a first predetermined amount and any memory cell has been erased less than a second predetermined amount has been met. If the condition has been met, erasing is continued by applying the erase pulse to the block having the memory cell with the condition independently of the other blocks of the plurality of blocks.

Abstract: A technique for detecting a leaky bit of a non-volatile memory includes erasing cells of a non-volatile memory. A bias stress is applied to the cells subsequent to the erasing. An erase verify operation is performed on the cells subsequent to the applying a bias stress to the cells. Finally, it is determined whether the cells pass or fail the erase verify operation based on whether respective threshold voltages of the cells are below an erase verify level.

Abstract: A sense amplifier is configured to sense a current from a selected bit cell of a non-volatile memory array and compare the sensed current to a reference current to determine a logic state stored in the bit cell. A controller is configured to perform a program/erase operation on at least a portion of the memory array to change a logic state of at least one bit cell of the portion of the memory array; determine a number of program/erase pulses applied to the at least one bit cell during the program/erase operation to achieve the change in logic state; and when the number of program/erase pulses exceeds a pulse count threshold, adjust the reference current of the sense amplifier for a subsequent program/erase operation.

Abstract: A sense amplifier is configured to sense a current from a selected bit cell of a non-volatile memory array and compare the sensed current to a reference current to determine a logic state stored in the bit cell. A controller is configured to perform a program/erase operation on at least a portion of the memory array to change a logic state of at least one bit cell of the portion of the memory array; determine a number of program/erase pulses applied to the at least one bit cell during the program/erase operation to achieve the change in logic state; and when the number of program/erase pulses exceeds a pulse count threshold, adjust the reference current of the sense amplifier for a subsequent program/erase operation.

Abstract: Methods and systems are disclosed for dynamic healing of non-volatile memory (NVM) cells within NVM systems. The dynamic healing embodiments described herein relax damage within tunnel dielectric layers for NVM cells that occurs over time from charges (e.g., holes and/or electrons) becoming trapped within these tunnel dielectric layers. NVM operations with respect to which dynamic healing processes can be applied include, for example, erase operations, program operations, and read operations. For example, dynamic healing can be applied where performance for the NVM system degrades beyond a selected performance level for an NVM operation, such as elevated erase/program pulse counts for erase/program operations and bit errors for read operations. A variety of healing techniques can be applied, such as drain stress processes, gate stress processes, and/or other desired healing techniques.

Abstract: Methods and systems are disclosed for extended erase protection for non-volatile memory (NVM) cells during embedded erase operations for NVM systems. The embodiments described herein utilize an additional threshold voltage (Vt) check after soft programming operation within an embedded erase operation completes to provide extended erase protection of NVM cells. In particular, the threshold voltages for NVM cells are compared against a threshold voltage (Vt) check voltage (VCHK) level and an additional embedded erase cycle is performed if any NVM cells are found to exceed the threshold voltage (Vt) check voltage (VCHK) level. The threshold voltage (Vt) check voltage (VCHK) level can be, for example, a voltage level that is slightly higher than an erase verify voltage (VEV) level and lower than read voltage level (VR).

Abstract: In accordance with at least one embodiment, a non-volatile memory (NVM) and method is disclosed for detecting latent slow erase bits. At least a portion of an array of NVM cells is erased with a reduced erase bias. The reduced erase bias has a reduced level relative to a normal erase bias. A least erased bit (LEB) threshold voltage level of the least erased bit (LEB) is determined. An erase verify is performed at an adjusted erase verify read threshold voltage level. The adjusted erase verify read threshold voltage level is a predetermined amount lower than the LEB read threshold voltage level. A number of failing bits is determined. The failing bits are bits with a threshold voltage above the adjusted erase verify level. The NVM is rejected in response to the number of failing bits being less than a failing bits threshold.

Abstract: A semiconductor device comprises an array of memory cells. Each of the memory cells includes a tunnel dielectric, a well region including a first current electrode and a second current electrode, and a control gate. The first and second current electrodes are adjacent one side of the tunnel dielectric and the control gate is adjacent another side of the tunnel dielectric. A controller is coupled to the memory cells. The controller includes logic to determine when to perform a healing process in the tunnel dielectric of the memory cells, and to apply a first voltage to the first current electrode of the memory cells during the healing process to remove trapped electrons and holes from the tunnel dielectric.