Patents by Inventor Fugang CHEN

Fugang CHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240098902
    Abstract: Disclosed are a thermoforming device and method for a flexible printed circuit board. The thermoforming device may include: a first forming mechanism provided with a first forming portion, the first forming portion being configured to carry the flexible printed circuit board to be processed; a second forming mechanism provided with a second forming portion which matches with the first forming portion, at least one of the first forming portion or the second forming portion is provided with a corresponding heating module configured for heat treatment of the flexible printed circuit board; a first driving mechanism configured to drive the first forming mechanism and the second forming mechanism to be displaced relative to each other in a first direction; a second driving mechanism configured to drive the second forming mechanism and the first forming mechanism to be displaced relative to each other in a second direction perpendicular to the first direction; and a controller.
    Type: Application
    Filed: January 7, 2022
    Publication date: March 21, 2024
    Inventors: Da CHEN, Fengying WANG, Yiming LI, Fugang NIE, Zhe LIU, Feng WANG, Yichuo SHI
  • Patent number: 11658239
    Abstract: The present disclosure provides a semiconductor device and a fabrication method. The semiconductor device includes: a substrate; a first well region in the substrate, having first ions; an isolation layer in the first well region; a second well region and a third well region, formed in the first well region, located respectively on opposite sides of the isolation layer, having second ions with an opposite conductivity type as the first ions, and with a minimum distance from the isolation layer greater than zero; a first gate structure on the second well region and the first well region; a second gate structure on the third well region and the first well region; a barrier gate on the isolation layer, located between the first gate structure and the second gate structure, and having the second ions; and source-drain doped layers in the second well region and the third well region, respectively.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: May 23, 2023
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Xuemei Wang, Fugang Chen, Yun Xue
  • Patent number: 10784303
    Abstract: A CMOS image sensor includes a semiconductor substrate, a plurality of pixel regions in the semiconductor substrate, a deep trench disposed between two adjacent pixel regions and filled with a polysilicon layer doped a first conductivity type, a plurality of well regions having a second conductivity type in each of the pixel regions, a through hole connected to the polysilicon material, and an metal interconnect layer connected to the through hole. The deep trench filled with the doped polysilicon layer completely isolates adjacent pixel regions. A voltage applied to the metal interconnect layer extracts excess photoelectrons generated by intensive incident light to improve the performance of the CMOS image sensor.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: September 22, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Fugang Chen, Wenlei Chen, Jie Ru
  • Publication number: 20200251589
    Abstract: The present disclosure provides a semiconductor device and a fabrication method. The semiconductor device includes: a substrate; a first well region in the substrate, having first ions; an isolation layer in the first well region; a second well region and a third well region, formed in the first well region, located respectively on opposite sides of the isolation layer, having second ions with an opposite conductivity type as the first ions, and with a minimum distance from the isolation layer greater than zero; a first gate structure on the second well region and the first well region; a second gate structure on the third well region and the first well region; a barrier gate on the isolation layer, located between the first gate structure and the second gate structure, and having the second ions; and source-drain doped layers in the second well region and the third well region, respectively.
    Type: Application
    Filed: January 10, 2020
    Publication date: August 6, 2020
    Inventors: Xuemei WANG, Fugang CHEN, Yun XUE
  • Publication number: 20170207270
    Abstract: A CMOS image sensor includes a semiconductor substrate, a plurality of pixel regions in the semiconductor substrate, a deep trench disposed between two adjacent pixel regions and filled with a polysilicon layer doped a first conductivity type, a plurality of well regions having a second conductivity type in each of the pixel regions, a through hole connected to the polysilicon material, and an metal interconnect layer connected to the through hole. The deep trench filled with the doped polysilicon layer completely isolates adjacent pixel regions. A voltage applied to the metal interconnect layer extracts excess photoelectrons generated by intensive incident light to improve the performance of the CMOS image sensor.
    Type: Application
    Filed: December 16, 2016
    Publication date: July 20, 2017
    Inventors: FUGANG CHEN, Wenlei Chen, Jie Ru
  • Publication number: 20160093649
    Abstract: A method for manufacturing a semiconductor device may include the following steps: preparing a substrate; providing a gate material layer that overlaps the substrate; providing a blocking layer that partially covers the gate material layer; removing a portion of the gate material layer that is not covered by the blocking layer for forming a gate electrode; providing a blocking material layer that covers both the blocking layer and the substrate; removing a portion of the blocking material layer for forming a blocking member that has an opening, wherein the opening partially exposes the blocking layer and partially exposes the substrate; and performing ion implantation through the opening to form a doped well region in the substrate.
    Type: Application
    Filed: September 24, 2015
    Publication date: March 31, 2016
    Inventors: Xuemei WANG, Fugang CHEN, Shuaibing LIN, Feng HUANG