Abstract: The present disclosure provides a method and system for constructing a digital rock, and relates to the technical field of digital rocks. According to the method, a three-dimensional (3D) digital rock image that can reflect real rock information is obtained using an image scanning technology, and the image is preprocessed to obtain a digital rock training image for training a generative adversarial network (GAN). The trained GAN is stored to obtain a digital rock construction model. The stored digital rock construction model can be directly used to quickly construct a target digital rock image. This not only greatly reduces computational costs, but also reduces costs and time consumption for obtaining high-resolution sample images. In addition, the constructed target digital rock image can also reflect real rock information.

Abstract: A connection is established between an access terminal and a first radio network controller through a first radio node. The first radio node is controllable primarily by the first radio network controller. The connection is maintained with the first radio network controller as the access terminal moves from a coverage area of the first radio node toward a coverage area of a second radio node. The second radio node is controllable primarily by a second radio network controller and controllable subordinately by the first radio network controller. A connection is also established through the second radio node. Upon a fulfillment of a predetermined criterion, the connection is transferred from the first radio network controller to the second radio network controller.

Abstract: Improved instruction set and core design, control and communication for programmable microprocessors is disclosed, involving the strategy for replacing centralized program sequencing in present-day and prior art processors with a novel distributed program sequencing wherein each functional unit has its own instruction fetch and decode block, and each functional unit has its own local memory for program storage; and wherein computational hardware execution units and memory units are flexibly pipelined as programmable embedded processors with reconfigurable pipeline stages of different order in response to varying application instruction sequences that establish different configurations and switching interconnections of the hardware units.

Abstract: The invention resides in a flexible data pipeline structure for accommodating software computational instructions for varying application programs and having a programmable embedded processor with internal pipeline stages the order and length of which varies as fast as every clock cycle based on the instruction sequence in an application program preloaded into the processor, and wherein the processor includes a data switch matrix selectively and flexibly interconnecting pluralities of mathematical execution units and memory units in response to said instructions, and wherein the execution units are configurable to perform operations at different precisions of multi-bit arithmetic and logic operations and in a multi-level hierarchical architecture structure.

Abstract: Improved instruction set and core design, control and communication for programmable microprocessors is disclosed, involving the strategy for replacing centralized program sequencing in present-day and prior art processors with a novel distributed program sequencing wherein each functional unit has its own instruction fetch and decode block, and each functional unit has its own local memory for program storage; and wherein computational hardware execution units and memory units are flexibly pipelined as programmable embedded processors with reconfigurable pipeline stages of different order in response to varying application instruction sequences that establish different configurations and switching interconnections of the hardware units.

Abstract: The invention resides in a flexible data pipeline structure for accommodating software computational instructions for varying application programs and having a programmable embedded processor with internal pipeline stages the order and length of which varies as fast as every clock cycle based on the instruction sequence in an application program preloaded into the processor, and wherein the processor includes a data switch matrix selectively and flexibly interconnecting pluralities of mathematical execution units and memory units in response to said instructions, and wherein the execution units are configurable to perform operations at different precisions of multi-bit arithmetic and logic operations and in a multi-level hierarchical architecture structure.

Abstract: A connection is established between an access terminal and a first radio network controller through a first radio node. The first radio node is controllable primarily by the first radio network controller. The connection is maintained with the first radio network controller as the access terminal moves from a coverage area of the first radio node toward a coverage area of a second radio node. The second radio node is controllable primarily by a second radio network controller and controllable subordinately by the first radio network controller. A connection is also established through the second radio node. Upon a fulfillment of a predetermined criterion, the connection is transferred from the first radio network controller to the second radio network controller.

Abstract: Data packets are received by the REDP traffic conditioning marker from the upstream domain and each have a red, yellow, or green priority level. The traffic conditioning marker monitors the rate of green data packets flowing through the A random early demotion and promotion (REDP) traffic conditioning marker is located between an upstream domain and a downstream domain. If the rate exceeds a negotiated rate, the traffic conditioner randomly and fairly demotes green packets to yellow. If the rate is less than the negotiated rate, the traffic conditioner randomly and fairly promotes yellow packets to green. The traffic conditioner removes the phase effects that occur in conventional markers.